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A new technique and CMOS VLSI implementation for computing approxlmate logarithms (base 2, and 10) for binary integers is presented. The approximation is performed using only combinational logic and requires no multiplications. Additionally, as implemented a ROM of only N x logp ( N ) bits is used to convert N bit integers. The maximum error of the approximation is 1.5% when the input value is 3, and decays exponentially to less than 0.5% for input values greater than 25.

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Novel quaternary logic circuits, designed in 2-u.m'CMOS technology, are presented. These include threshold detector circuits with an improved output voltage swing and a simple binary-to-quaternary encoder circuit. Based on these, the literal circuits, the quaternary-tobinary decoder, and the quaternary register designs are derived. A novel scheme for improving the power-delay product of pseudo-NMOS circuits is developed. Simulations for an inverter indicate a 66% improvement over a conventional pseudo-NMOS circuit. Noise-margin and tolerance estimations are made for the threshold detectors. To demonstrate the utility of these circuits, a quaternary sequential/storage logic array (QSLA), based on the Allen-Givone algebra, has been designed and fabricated. The prototype chip occupies an area of 4.84 mm 2 , is timed with a 2.2-MHz clock, and consumes 93 mW of power.

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