VLSI Implementations of Low-Power Leading-One Detector Circuits

Abed, K.H.; Siferd, R.

doi:10.1109/second.2006.1629364

Cited by 20 publications

(8 citation statements)

References 12 publications

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“…The proposed architecture of the 4-bit LOD is simple in comparison as well as with less hardware requirement. It is easily observed that the proposed design is efficient in comparison of reported design [5][6]31]. [37,38] The proposed 8, 16 and 32 bits LOD having a serial connection in arrangement from the MSB 'dn-1' to the LSB 'd0' in comparison of reported LSB d0 to the MSB dn-1.…”

Section: Leading One Detectormentioning

confidence: 99%

“…Logarithmic operations can be converted multiplications operation into additions and divisions into subtractions, respectively, which can save a lot of computation efforts. Leading-One Detector (LOD) design becomes important due to the normalization process in logarithmic multiplication and logarithmic converter [4][5][6]. It is used in logarithmic converters to find the position of the leading one bit with the integral and the fractional parts of a logarithm operation.…”

Section: Introductionmentioning

confidence: 99%

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An efficient architecture of iterative logarithm multiplier

Nandan¹,

Kanungo²,

Mahajan³

2018

IJET

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Multiplication is one of important arithmetic component for digital signal processing, neural network and image processing. But, it is well known fact that multiplier has most hardware consuming component out of all arithmetic components. Here, it is given a possible solution by using an efficient VLSI architecture of Mitchell's algorithm based Iterative Logarithmic Multiplier (ILM) with modified architecture of Leading One Detector (LOD) and seamless pipelined technique. The proposed work is based on the hardware minimization at the same error cost than of previously reported architectures. We use VHDL to design the existing and proposed Mitchell's algorithm based iterative logarithmic multiplier. Both multipliers design are evaluated with the Synopsys design compiler by using 90 nm CMOS technology and compared the results in terms of Data Arrival Time (DAT), area, power, Area Delay Product (ADP) and energy. The proposed Mitchell's based ILM gives 33.18 %, 39.03 % and 31.62 % less ADP, 25.08 %, 38.08 % and 46.72 % less energy for 8, 16, and 32 bits architecture respectively in comparison of the reported ILM. The importance of LODs and seamless pipeline has been shown in an efficient architecture of Mitchell's based ILM.

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Section: Leading One Detectormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An efficient architecture of iterative logarithm multiplier

Nandan¹,

Kanungo²,

Mahajan³

2018

IJET

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“…Generally, we could calculate the scaling factor and the rotation operation separately. The rotation operation was carried out according to (7).…”

Section: Schematic Of Cordic Algorithm Rotationmentioning

confidence: 99%

“…In Table 3, the maximum range of rotation angle is -99.88° ≤ θ ≤ 99.88°, which could not achieve a complete cycle. To make sure that CORDIC algorithm is convergence, the sum of rotation angles must be bigger than the angle of rotation which is actually required, and the input angle should must be pretreated [7]. …”

mentioning

confidence: 99%

An Optimization of CORDIC Algorithm and FPGA Implementation

Rui

Jiang²,

Huang

et al. 2015

IJHIT

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“…This method can accelerate the design, but it does not introduce the circuit optimisation due to the restriction of already-defined logic gates in PLAs. For the very-large-scale integration (VLSI) circuit design, the leading-one detector is widely used for determining both the integer part and fraction part [15][16][17]. The leading-one detector ( Fig.…”

Section: Introductionmentioning

confidence: 99%

Calibration method to reduce the error in logarithmic conversion with its circuit implementation

Zhao

Srivastava

Peng

et al. 2018

IET Circuits, Devices & Systems

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Here, based on Mitchell's logarithmic conversion, the authors propose a fast calibration method using a fixed binary code with case judgement, which suppresses the conversion error. The authors developed a highly paralleled circuit serving the proposed calibration method. Differential cascade voltage switch logic (DCVSL) is used to work in both high-speed logic and adiabatic logic and trade-off between power dissipation and operation speed. In addition, a low-cost adiabatic clock generator without any passive component is presented to support a four-phase sine clock for the adiabatic logic operation. An 8-bit logarithmic converter is designed in TSMC 180 nm CMOS. Post-simulation results show that the proposed calibration can reduce the conversion error to 1.55% based on Mitchell's algorithm, the power dissipation varies between 1.12 and 3.709 mW, and the delay is 1.82 ns under operational DCVLS.

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VLSI Implementations of Low-Power Leading-One Detector Circuits

Cited by 20 publications

References 12 publications

An efficient architecture of iterative logarithm multiplier

An efficient architecture of iterative logarithm multiplier

An Optimization of CORDIC Algorithm and FPGA Implementation

Calibration method to reduce the error in logarithmic conversion with its circuit implementation

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