A version control approach to Cache coherence

Cheong, Hoichi; Veidenbaum, Alexander V.

doi:10.1145/318789.318824

Cited by 25 publications

(10 citation statements)

References 11 publications

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“…Versioning has also been used to speed up the invalidation process and to dynamically identify which cache lines need to be invalidated [7,21]. In [7] the authors propose associating each cache line with two counters.…”

Section: Coherence Based On Data Versioningmentioning

confidence: 99%

“…In [7] the authors propose associating each cache line with two counters. One is called a birth version number (bvn) and is stored on the cache line, the other is called a Current Version Number (CVN), which is a global (per CPU) counter that represents the current version of the line.…”

Section: Coherence Based On Data Versioningmentioning

confidence: 99%

“…In particular [7] increments the counters much more frequently, i.e., any time it is possible that a shared variable is modified. It also requires significantly more storage dedicated to version counters because it requires two counters per cache line, and they are typically larger than the counter values we use (to prevent frequent overflows), whereas we require only one counter per cache line and one per each TLB entry (which typically has far fewer entries than the cache).…”

Section: Coherence Based On Data Versioningmentioning

confidence: 99%

See 2 more Smart Citations

Lazy cache invalidation for self-modifying codes

Gutierrez

Pusdesris

Dreslinski

et al. 2012

Proceedings of the 2012 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

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Just-in-time compilation with dynamic code optimization is often used to help improve the performance of applications that utilize high-level languages and virtual run-time environments, such as those found in smartphones. Justin-time compilation introduces additional overhead into the instruction fetch stage of a processor that is particularly problematic for user applications-instruction cache invalidation due to the use of self-modifying code. This softwareassisted cache coherence serializes cache line invalidations, or causes a costly invalidation of the entire instruction cache, and prevents useful instructions from being fetched for the period during which the stale instructions are being invalidated. This overhead is not acceptable for user applications, which are expected to respond quickly.In this work we introduce a new technique that can, using a single instruction, invalidate cache lines in page-sized chunks as opposed to invalidating only a single line at a time. Lazy cache invalidation reduces the amount of time spent stalling due to instruction cache invalidation by removing stale instructions on demand as they are accessed, as opposed to all at once. The key observation behind lazy cache invalidation is that stale instructions do not necessarily need to be removed from the instruction cache; as long as it is guaranteed that attempts to fetch stale instructions will not hit in the instruction cache, the program will behave as the developer had intended.

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Section: Coherence Based On Data Versioningmentioning

confidence: 99%

Section: Coherence Based On Data Versioningmentioning

confidence: 99%

Section: Coherence Based On Data Versioningmentioning

confidence: 99%

See 1 more Smart Citation

Lazy cache invalidation for self-modifying codes

Gutierrez

Pusdesris

Dreslinski

et al. 2012

Proceedings of the 2012 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

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“…Several compiler-directed cache coherence schemes 10,12,13,14,18,21,29,30] have been recently proposed. These schemes give better performance, but demand more hardware and compiler support than the previous schemes.…”

Section: Introductionmentioning

confidence: 99%

Hardware and compiler-directed cache coherence in large-scale multiprocessors: Design considerations and performance study

Choi

Yew

2000

IEEE Trans. Parallel Distrib. Syst.

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In this paper, we study a hardware-supported, compiler-directed (HSCD) cache coherence scheme, which can be implemented on a large-scale multiprocessor using o -the-shelf microprocessors, such as the Cray T3D. The scheme can be adapted to various cache organizations, including multi-word cache lines and byte-addressable architectures. Several system related issues, including critical sections, inter-thread communication, and task migration have also been addressed. The cost of the required hardware support is minimal and proportional to the cache size. The necessary compiler algorithms, including intra-and interprocedural array data ow analysis, have been implemented on the Polaris parallelizing compiler 33].From our simulation study using the Perfect Club benchmarks 5], we found that in spite of the conservative analysis made by the compiler, the performance of the proposed HSCD scheme can be comparable to that of a full-map hardware directory scheme. Given its comparable performance and reduced hardware cost, the proposed scheme can be a viable alternative for large-scale multiprocessors such as the Cray T3D, which rely on users to maintain data coherence.

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“…The exploitation of inter-epoch locality requires either a more sophisticated compile-time analysis [9,101 or additional hardware [8,211. The compile-time analysis method does not require any additional hardware but suffers performance problems arising from the conservative approach taken by the compiler due to the lack of execution time information.…”

Section: Introductionmentioning

confidence: 99%

An efficient caching support for critical sections in large-scale shared-memory multiprocessors

Min

Baer

Kim

1990

SIGARCH Comput. Archit. News

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Directory-basedand software-assisted schemes are the two main approaches to solving the cache co-PermissIon to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the ACM copytight notice and the title of the publication and its date appear, and notice Is given that copyln~ 18 by permission of the Association for Computing Machinery. To copy otherwise, or to republish, requlfes a fee and/or specific permission. 0 lgs0

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A version control approach to Cache coherence

Cited by 25 publications

References 11 publications

Lazy cache invalidation for self-modifying codes

Lazy cache invalidation for self-modifying codes

Hardware and compiler-directed cache coherence in large-scale multiprocessors: Design considerations and performance study

An efficient caching support for critical sections in large-scale shared-memory multiprocessors

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