Software-assisted cache coherence enforcement schemes for large multiprocensor systams with shared global memory and interconnection network have gained increasing attention. P r o p o d softwareaasisted approaches rely on either indiscriminate invalidation or selective invalidation to invalidate stale cache lines. The indiscriminate approach combined with advanced memory hardware can quickly invalidate the entire cache but may result in lower hit ratios. The selective approach may achieve a better hit ratio. However, sequential selection and invalidation of cache or TLB entries is time consuming. We propoae a new solution that offers the fast operation of the indiscriminate invalidation approach and can selectively invalidate cache items without extensive run-time book-keeping and checking. The solution relies on the combination of compiletime reference tagging and individual invalidation of potentially stale cache lines only when referenced. Paformance improvement over an indiscriminate invalidation approach is presented.

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n this paper, a cache coherence strategy with u combinzd sofhvare and hardware approach is proposed for large-scale multiprocessor systems. The new strategy has the scalability advantages of existing software strategies and does trot rely on shared hardware resources to maitiain coherence. it exploits as much intra-task temporal locality as previously propo,red low-cost, compiler-based strategies such as Simple Invalidation and Fast Selective Invalidation. With a small amount of additional hardware and a small set of cache management irr.rtructions, the rww strategy preserves more inter-task-level temporal locali~y than~hese stra~e-gies. It is an economical alternative and has potential performance close to that of more elaborate strategies such m Version Control and Time Stanp. Also, the new strategy is easily exterrdable to include Doa c ross loops.

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