A vertical-gaussian doped soi-tfet with enhanced dc and analog/rf performance

Ehteshamuddin, M.; Loan, Sajad A.; Rafat, M.

doi:10.1088/1361-6641/aac97d

Cited by 29 publications

(8 citation statements)

References 32 publications

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“…The Id Vs Vds characteristics of USD-TFET with different types of materials such as Hafnium Oxide (HfO2), Silicon(Si), and Silicon Dioxide (SiO2) [24], are found in this construction. The drain current of USD-TFET increased when compared to the other devices as shown in Figure 7.…”

Section: Drain Current Characteristicsmentioning

confidence: 99%

Design and Analysis of Hetero Dielectric Dual Material Gate Underlap Spacer Tunnel Field Effect Transistor

Howldar,

Balaji,

Srinivasa Rao

2023

IJE

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Section: Drain Current Characteristicsmentioning

confidence: 99%

Design and Analysis of Hetero Dielectric Dual Material Gate Underlap Spacer Tunnel Field Effect Transistor

Howldar,

Balaji,

Srinivasa Rao

2023

IJE

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“…In all simulations, gate leakage current is ignored. Also, quantum confinement effect was not included according to the reported results in [28] which indicate that quantum confinement effects are prominent only below t Si of 7 nm.…”

Section: Device Structure and Parametersmentioning

confidence: 99%

A comprehensive investigation of TFETs with semiconducting silicide source: impact of gate drain underlap and interface traps

Elnaggar

Shaker

Fedawy

2019

Semicond. Sci. Technol.

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In this paper, we have investigated the effect of gate underlap, while using semiconducting silicide material as a source region, on the ambipolar and high-frequency performance of Tunnel Field Effect Transistors (TFETs). We demonstrated how to suppress the ambipolar conduction and enhance the ON current without deteriorating the performance of high-frequency switching characteristics of the double gate TFET by using the combined two methods. The ON to OFF current ratio (I ON /I OFF ) and subthreshold swing (SS) as figures of merit for DC performance have been investigated. The main analog performance parameters like the transconductance (g m ) and unit-gain cutoff frequency ( f T ) are analyzed. Moreover, circuit level digital performance parameters like the fall propagation delay (t phl ) and overshoot voltage (V p ) are inspected when the proposed design is utilized in an inverter circuit. Impact of effective oxide thickness and traps arising from manufacturing process on DC, analog, and circuit level performance is also investigated. TCAD simulation results reveal a significant enhancement in DC, analog and digital performance parameters of the proposed heterojunction TFET over Si-TFET that makes the proposed design more advantageous in the field of analog and digital applications.

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“…However, regardless of the materials [8,9], designs [10,11], or specific fabrication procedures [12,13] employed to improve tunneling likelihood, attaining a steep slope with a significant I ON current has proven extremely difficult. Although most research has concentrated on TFETs for low-power applications, a few studies suggest that they can also be used in analog/RF circuits [14][15][16][17][18][19]. When used in low-power switching and analog/RF applications, the V TH , SS, and I OFF of a device should be low, while the I ON , I ON /I OFF , g m , f T , GBP, and other characteristics should be high.…”

Section: Introductionmentioning

confidence: 99%

Investigation of electrical parameters and temperature analysis of a dual-metal DG PNPN TFET with extended source

Baruah

Baishya

2023

Eng. Res. Express

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In this article, a dual-metal double-gate extended-source PNPN tunnel-FET (DG-ES-DMG TFET) is proposed and investigated. The performance of conventional double-gate PNPN TFET (DG TFET) can be improved by extending a portion of the source to the channel side, which creates vertical tunneling along with the lateral tunneling, thereby enhancing the band-to-band tunneling rate and on-current in double-gate extended-source PNPN tunnel-FET (DG-ES TFET). The performance of this DG-ES TFET can be further enhanced by introducing a dual metal gate in DG-ES-DMG TFET. The performance of the TFETs is evaluated with the help of TCAD (Technology Computer-Aided Design) software. The proposed optimized DG-ES-DMG TFET provides very good performances; On-current (ION) of 1.39 x 10-3 A/µm, On-Off current ratio (ION/IOFF) of 1.10 x 1011, subthreshold swing (SS) of 20 mV/Decade, threshold voltage (VTH) of 0.37 V, and a cut-off frequency (fT) of 188 GHz. The temperature sensitivity of the TFETs is also analyzed in this work. The comparison of the proposed TFET with other existing TFETs reveals that the proposed TFET could be a good contender for low-power applications.

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A vertical-gaussian doped soi-tfet with enhanced dc and analog/rf performance

Cited by 29 publications

References 32 publications

Design and Analysis of Hetero Dielectric Dual Material Gate Underlap Spacer Tunnel Field Effect Transistor

Design and Analysis of Hetero Dielectric Dual Material Gate Underlap Spacer Tunnel Field Effect Transistor

A comprehensive investigation of TFETs with semiconducting silicide source: impact of gate drain underlap and interface traps

Investigation of electrical parameters and temperature analysis of a dual-metal DG PNPN TFET with extended source

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