A very low column FPN and row temporal noise 8.9 M-pixel, 60 fps CMOS image sensor with 14bit column parallel SA- ADC

Matsuo, Shin’ichiro; Bales, Tim; Shoda, Makoto; Osawa, Shinji; Almond, B.; Mo, Yaowu; Gleason, J.; Chow, T.W.; Takayanagi, Isao

doi:10.1109/vlsic.2008.4585983

Cited by 30 publications

(11 citation statements)

References 4 publications

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“…They are not suitable for high-speed image sensors. The SAR ADCs [23,29] offer good performance, with pitches of 4.2 and 2.25 μm, respectively. However, they can be integrated with very fine pitches, and this makes them popular.…”

Section: Adc Comparisonmentioning

confidence: 99%

“…Although SAR ADCs require a DAC per column, whose area is large for consumer electronics with a fine pixel pitch, they have been adapted and optimized for column-parallel topologies offering very competitive solutions [23,29], according to our FoM. Modern implementations achieve a fine pitch, a good resolution, and a low power consumption.…”

Section: Qualification Of Different Adc Architecturesmentioning

confidence: 99%

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Low-Noise Detectors through Incremental Sigma–Delta ADCs

Leñero‐Bardallo¹,

Rodríguez-Vázquez²

2017

Analog Electronics for Radiation Detection

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Section: Adc Comparisonmentioning

confidence: 99%

Section: Qualification Of Different Adc Architecturesmentioning

confidence: 99%

Low-Noise Detectors through Incremental Sigma–Delta ADCs

Leñero‐Bardallo¹,

Rodríguez-Vázquez²

2017

Analog Electronics for Radiation Detection

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“…A column-parallel analog-to-digital converter (ADC) [8][9][10][11][12][13] in CMOS imagers is one of the important techniques to meet these requirements. For reading image signals from image array with low noise and wide dynamic range, the column-parallel folding-integration/cyclic ADC is used [14,15].…”

Section: B Column-parallel Readout Circuitmentioning

confidence: 99%

A high fill-factor low dark leakage CMOS image sensor with shared-pixel design

et al. 2014

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We have developed and evaluated the high responsivity and low dark leakage CMOS image sensor with the ring-gate shared-pixel design. A ring-gate shared-pixel design with a high fill factor makes it possible to achieve the low-light imaging. As eliminating the shallow trench isolation in the proposed pixel, the dark leakage current is significantly decreased because one of major dark leakage sources is removed. By sharing the in-pixel transistors such as a reset transistor, a select transistor, and a source follower amplifier, each pixel has a high fill-factor of 43 % and high sensitivity of 144.6 ke -/lx·sec. In addition, the effective number of transistors per pixel is 1.75. The proposed imager achieved the relatively low dark leakage current of about 104.5 e -/s (median at 60°C), corresponding to a dark current density J dark_proposed of about 30 pA/cm 2 . In contrast, the conventional type test pixel has a large dark leakage current of 2450 e -/s (median at 60°C), corresponding to J dark_conventional of about 700 pA/cm 2 . Both pixels have a same pixel size of 7.5×7.5 μm 2 and are fabricated in same process.

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“…But it also suffers from the noise deterioration [23,24], especially the Fixed Pattern Noise (FPN) because of the large layout area penalty [25][26][27][28][29][30]. The signal data is transferred to the column processor and subtracted from the previously stored reset level data to provide FPN correction, designed in [31], which will occupy the readout cycle. A simple way to attenuate FPN in the three-FET APS operating in the wide-dynamic-range logarithmic mode was proposed in [32], which only requires the drain terminal of the reset transistor to be available.…”

Section: Introductionmentioning

confidence: 99%

An improved segmented DAC for column readout circuit correction of large array CMOS image sensor

Guo

2020

IEICE Electron. Express

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The non-ideal factors and error sources of segmented DAC for multi-channel large array CMOS image sensor are given. An improved precise segmented DAC using adaptive switching technology is proposed. This scheme has been verified on a 50mm×50mm large array CMOS image sensor prototype chip, which consisting of 8320× 8320 pixel array was designed and fabricated in 55nm CMOS 1P4M standard process. The measurement results show that the DNL of DAC can be reduced from 33 LSBs of traditional structure to within 0.5LSB, and the large array sensor chip reaches a high intrinsic dynamic range of 75dB, a low FPN of 0.06%, and a low photo response nonuniformity of 1.5% respectively. Finally, a good raw image is taken by the prototype sensor.

show abstract

A very low column FPN and row temporal noise 8.9 M-pixel, 60 fps CMOS image sensor with 14bit column parallel SA- ADC

Cited by 30 publications

References 4 publications

Low-Noise Detectors through Incremental Sigma–Delta ADCs

Low-Noise Detectors through Incremental Sigma–Delta ADCs

A high fill-factor low dark leakage CMOS image sensor with shared-pixel design

An improved segmented DAC for column readout circuit correction of large array CMOS image sensor

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