A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores

J. Emerg. Technol. Comput. Syst.

2015

Networks-on-chip (NoCs) are a widely recognized viable interconnection paradigm to support the multicore revolution. One of the major design issues of multicore architectures is still the power, which can no longer be considered mainly due to the cores, since the NoC contribution to the overall energy budget is relevant. To face both static and dynamic power while balancing NoC performance, different actuators have been exploited in literature, mainly dynamic voltage frequency scaling (DVFS) and power gating. Typically, simulation-based tools are employed to explore the huge design space by adopting simplified models of the components. As a consequence, the majority of state-of-the-art on NoC power-performance optimization do not accurately consider timing and power overheads of actuators, or (even worse) do not consider them at all, with the risk of overestimating the benefits of the proposed methodologies.This article presents a simulation framework for power-performance analysis of multicore architectures with specific focus on the NoC. It integrates accurate power gating and DVFS models encompassing also their timing and power overheads. The value added of our proposal is manyfold: (i) DVFS and power gating actuators are modeled starting from SPICE-level simulations; (ii) such models have been integrated in the simulation environment; (iii) policy analysis support is plugged into the framework to enable assessment of different policies; (iv) a flexible GALS (globally asynchronous locally synchronous) support is provided, covering both handshake and FIFO re-synchronization schemas. To demonstrate both the flexibility and extensibility of our proposal, two simple policies exploiting the modeled actuators are discussed in the article.

“…✓ ✓ ✓ run-time control [Bartolini et al 2010] policies for multicores reliability/perf for multicores Carlson et al (Sniper) [Carlson et al 2011] [Prabhu et al 2009] schemes for NoC…”

Section: Hsieh Et Al (Sst)mentioning

confidence: 99%

Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators

J. Emerg. Technol. Comput. Syst.

2015

“…Bartolini et al [2] proposes a framework to evaluate different thermal policies based on control theory. Even if they support the DVFS, the framework lacks of an accurate evaluation of the PLL model as well as the implementation of the DVFS for the on-chip network.…”

Section: Simulation Frameworkmentioning

confidence: 99%

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

Terraneo

Journal of Systems Architecture

2015

a b s t r a c tNetworks-on-Chip (NoCs) are considered a viable solution to fully exploit the computational power of multi-and many-cores, but their non negligible power consumption requires ad hoc power-performance design methodologies. In this perspective, several proposals exploited the possibility to dynamically tune voltage and frequency for the interconnect, taking steps from traditional CPU-based power management solutions. However, the impact of the actuators, i.e. the limited range of frequencies for a PLL (Phase Locked Loop) or the time to increase voltage and frequency for a Dynamic Voltage and Frequency Scaling (DVFS) modules, are often not carefully accounted for, thus overestimating the benefits. This paper presents a control-based methodology for the NoC power-performance optimization exploiting the Dynamic Frequency Scaling (DFS). Both timing and power overheads of the actuators are considered, thanks to an ad hoc simulation framework. Moreover the proposed methodology eventually allows for user and/or OS interactions to change between different high level power-performance modes, i.e. to trigger performance oriented or power saving system behaviors. Experimental validation considered a 16-core architecture comparing our proposal with different settings of threshold-based policies. We achieved a speedup up to 3 for the timing and a reduction up to 33.17% of the power ⁄ time product against the best threshold-based policy. Moreover, our best control-based scheme provides an averaged power-performance product improvement of 16.50% and 34.79% against the best and the second considered threshold-based policy setting.

“…Their work focuses on large-scale systems, but application traces are emulated, rather than collected from cycle-accurate simulation, with higher simulation rate at the cost of much lower accuracy. Power and thermal models, as well as measurements from real hardware are used in the proposal of [10] based on the Simics functional simulator. The interesting achievement in this approach lies on the possibility to develop, analyze and tune different control algorithms for thermal and power management, based on high-level Matlab descriptions.…”

Section: A Related Workmentioning

confidence: 99%

A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures

Corbetta

2012 IEEE Computer Society Annual Symposium on VLSI

2012

Abstract-The increasing complexity of multi-core architectures demands for a comprehensive evaluation of different solutions and alternatives at every stage of the design process, considering different aspects at the same time. Simulation frameworks are attractive tools to fulfil this requirement, due to their flexibility. Nevertheless, state-of-theart simulation frameworks lack a joint analysis of power, performance, temperature profile and reliability projection at system-level, focusing only on a specific aspect. This paper presents a comprehensive estimation framework that jointly exploits these design metrics at system-level, considering processing cores, interconnect design and storage elements. We describe the framework in details, and provide a set of experiments that highlight its capability and flexibility, focusing on temperature and reliability analysis of multi-core architectures supported by Network-on-Chip interconnect.