A VLIW processor with reconfigurable instruction set for embedded applications

Abstract

This paper describes a new architecture for embedded reconfigurable computing, based on a very-long instruction word (VLIW) processor enhanced with an additional run-time configurable datapath. The reconfigurable unit is tightly coupled with the processor, featuring an application-specific instruction-set extension. Mapping computation intensive algorithmic portions on the reconfigurable unit allows a more efficient elaboration, thus leading to an improvement in both timing performance and power consumption. A test chip has been implemented in a standard 0.18-m CMOS technology. The test of a signal processing algorithmic benchmark showed speedups ranging from 4.3 to 13.5 and energy consumption reduced up to 92%.

Using 3D integration technology to realize multi-context FPGAs

“…3. We can calculate the area of the tile width in comparison to pitch and copper bond size: pitch_width = bond_width + spacing_width (8) tile_width = 3 × bond_width + 2 × spacing_width (9) tile_height = 3 × bond_width + 2 × spacing_width (10) A tile = tile_width × tile_height (11) We make the following simplifying assumptions: bond_width = bond_height (12) spacing_width = spacing_height (13) num_horizontal_bonds = num_vertical_bonds (14) From these assumptions, we can replace Eq. (11) with (15) …”

“…2D multi-context FPGAs have followed [3,9,10,[16][17][18]. These designs are all 2D, so the extra storage increases the planar area of each tile; this reduces logic density and increases wirelength, thereby degrading performance.…”

“…Historically, the latency of dynamic reconfiguration has been prohibitive; nonetheless, interest in techniques to speed up the reconfiguration of FPGAs remains. Multi-context FPGAs store several configurations on chip, switching between them at runtime [3,9,10,[16][17][18]; however, this reduces logic density and increases power consumption and wirelength.…”

Customizing the Datapath and ISA of Soft VLIW Processors

“…Companies like ARC and Tensilica have long been offering configurable and customizable processors along with supporting tool chains [6,7]. Academic researchers have also been embedding FPGA-like reconfigurable functional units (RFUs) in processor datapaths to implement custom instructions [8,9], and customizable co-processors to offload performancecritical computations from their host processors [10]. However, most customizable processors are also aimed at the ASIC market, making them difficult to recustomize once they have been manufactured; and RFUs are often constrained by fixed architectures that limit the range of custom operations they can support.…”

Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling

“…The XTENSA chip from Tensilica, the CHIMAERA [2] project, and the PRISC processor [7] use reconfigurable functional units within the processor pipeline. The PiCoGA architecture is a VLIW processor pipeline [5] with an additional pipelined reconfigurable architecture which works as a functional unit.…”