A VLSI architecture for real-time image coding using a vector quantization based algorithm

Dezhgosha, K.; Jamali, Mohsin M.; Kwatra, S.C.

doi:10.1109/78.157193

Cited by 23 publications

(7 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The high cost of communication in bit parallel circuits is very evident in the designs presented by both Davidson et al [13] and Dezhgosha [14]. In the super VQ tree architecture described by Dezhgosha et al [14], one can see that both the forward data path and backward control path require very large number of bus wires and their usage is quite low.…”

Section: Communicationmentioning

confidence: 94%

“…In the super VQ tree architecture described by Dezhgosha et al [14], one can see that both the forward data path and backward control path require very large number of bus wires and their usage is quite low. This is also reflected in their CDC (Codebook, Distortion and Comparison) module chip design where 52% of chip area has been occupied by interconnections and I/O pads.…”

Section: Communicationmentioning

confidence: 99%

“…In recent years, a number of VLSI architectures for VQ applications have been reported [11]- [14]. For example the authors have shown how bit serial, word parallel systolic Inner Product Array (IPA) circuits can be used in the construction of VQ full search and tree search systems [11] [12].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

VLSI architectures for vector quantization

Yan¹,

McCanny²,

Hu³

1995

Journal of VLSI Signal Processing

View full text Add to dashboard Cite

Abstract. The real time implementation of an efficient signal compression technique, Vector Quantization (VQ), is of great importance to many digital signal coding applications. In this paper, we describe a new family of bit level systolic VLSI architectures which offer an attractive solution to this problem. These architectures are based on a bit serial, word parallel approach and high performance and efficiency can be achieved for VQ applications of a wide range of bandwidths. Compared with their bit parallel counterparts, these bit serial circuits provide better alternatives for VQ implementations in terms of performance and cost.

show abstract

Section: Communicationmentioning

confidence: 94%

Section: Communicationmentioning

confidence: 99%

See 1 more Smart Citation

VLSI architectures for vector quantization

Yan¹,

McCanny²,

Hu³

1995

Journal of VLSI Signal Processing

View full text Add to dashboard Cite

show abstract

“…Early architectures used a pipeline of fast processors, where each processor executes part of the distortion measure [14], [15], while more recently, data parallelism was exploited by partitioning the codebook over a number of devices [16]. Although these approaches have achieved real-time performance, the solutions are expensive (typically requiring up to 100 chips), and inflexible.…”

Section: Ticementioning

confidence: 99%

Scalable vector quantization architecture for image compression

Cuhadar

Sampson²,

Downton³

Proceedings of 1996 IEEE Second International Conference on Algorithms and Architectures for Parallel Processing, ICA/sup 3/Pp

View full text Add to dashboard Cite

Vector quantization is a popular data compression technique due to its theoretical advantage over scalar quantization which enables exploitation of the dependencies between neighboring samples. However, the complexity of the encoding process imposes certain limitations on the size of the codebook population and/or the dimensions of the processed blocks. In this paper, we show that this complexity can be conveniently distributed as subcodebooks over general purpose MIMD parallel prccessors, to provide almost linearly scalable throughput and flexible configurability. A particular advantage of this approach is that it makes feasible the use of the higher dimensional image blocks and/or larger codebooks, leading to improved coding performance with no penalty in execution speed compared with the original sequential implementation. I INTRODUCTIONImage compression is an essential part of any imaging system. It aims to reduce the large amount of data required for storage and/or transmission of digital images and video. This is an important issue in applications such as high-definition TV, videoconferencing and video telephony [lI1 [Z].Vector quantization (VQ) h a s been extensively investigated for audio, speech, image and video coding applications [3], 241, [5]. The main advantage of using VQ-based compression algorithms is the simplicity of the decoding process. It typically involves a simple look-up table operation which makes VQ particularly useful for applications with single-encoder and multi-decoder systems. On the other hand, the major limitation of VQ is the high computational complexity required for the selection of the bestmatched codevector available in the VQ codebook. 'e-mail: cuhaa@gubim.bim.gantep.edu.tr, Fax: 90-342-3601100However, although the encoding task in VQ is computationally expensive, it is well suited for parallel processing because of the repetitive nature of the t a s k and the regularity of the image data. Conwage data volume and the computational complexity of the encoding task in VQ, the processing speed to meet this computational demand needs to be very large. Parallel processing has been a natural framework fdr fast image prccessing applications [6], [7]. In this paper, we present the application of a scalable parallel approach to the implementation of the VQ encoding process.This approach is based upon the pipeline processor farm (PPF) design methodology which has been developed for embedded image processing and computer vision applications [a], [9], [lo]. I1 VECTOR QUANTIZATIONVector quantization is a generalization of scalar quantization, where a group of samples are jointly quantized instead of individual quantization of each sample [5]. This offers the advantage that dependencies between neighboring data can be directly exploited. In general, a vector quantizer VQ of dimension k and size N can be defined as the mapping of the vtxtors or points of the k-dimensional Euclidean space Rk into a finite subset Y of N output points.That is, where Y = {yl E Rk; a = 1 2 . . . N ) is the set o...

show abstract

“…In the design of Ramamoorthy and Potu [SI, the system contains 2 chips, 32 PE's and 6 address generators and 6 comparors, are capable of handling real-time image encoding using VQ/multii-stage VQ with clock rate of 8-10 MHz. Dezhgosha et al[7] used less 100 VLSI/LSI chips to implement a VQ system, which is capable of real-time p r e cessing of 480x768 pixels per frame with refreshing rate of 30 frames/second in 25MHz. The bit rate is 1.12 bitsfpixel.…”

mentioning

confidence: 99%

A new multi-path tree-search FSVQ architecture for image/video sequence coding

Chao

Lee

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems

View full text Add to dashboard Cite

This paper presents a n e w multi-path tree-search architecture to implement various FSVQs for real-time image/video coding. The proposed architecture exploits the features used in both tree-search and An i t e state VQs and i n the mean time to adaptively update state codebooks so that PSNR is on the average 1dB-ZdB higher than that achieved from conventional FSVQs at the same bit rate. In particular, t h i s architecture can be pipelined in h a r d w a r e realization to overcome the iteration bounds as those encountered in conventional FSVQs, making it feasible to develop real-time cost-effective hardware solutions.

show abstract

A VLSI architecture for real-time image coding using a vector quantization based algorithm

Cited by 23 publications

References 10 publications

VLSI architectures for vector quantization

VLSI architectures for vector quantization

Scalable vector quantization architecture for image compression

A new multi-path tree-search FSVQ architecture for image/video sequence coding

Contact Info

Product

Resources

About