A VLSI chip implementation of an A/D converter error table compensator

Beaumont-Smith, A.; Tsimbinos, J.; Lim, Cheng‐Chew; Marwood, W.

doi:10.1016/s0920-5489(01)00064-2

Cited by 2 publications

(4 citation statements)

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“…This property can be used to reduce the hardware for the CRBBE circuit so that only one selector logic of each distinct signed multiple magnitude needs to be generated. The positive-negative-complement encoded RB partial product corresponding to the dipole, is denoted by as (8) where , and the subscripts and are the indexes of the multiplier and the multiplicand bits, respectively.…”

Section: A Radix-4 Covalent Redundant Binary Booth Encoding (Crbbe-2)mentioning

confidence: 99%

“…T HE digital multiplier is a ubiquitous arithmetic unit in microprocessors, digital signal processors, and emerging media processors [1]- [4]. It is also a kernel operator in application-specific data path of video and audio codecs, digital filters, computer graphics, and embedded systems [5]- [8]. Compared with many other arithmetic operations, multiplication is time-consuming and power hungry.…”

Section: Introductionmentioning

confidence: 99%

“…As 8-, 16-, 32-, and 64-b operands are pervasively used in application-specific data paths and multimedia and very long instruction word (VLIW) processors [1], [2], [5]- [8], [18], this paper focuses on power-of-two word-length RB multipliers to exploit the binary logarithmic partial product reduction rate of the RBA summing tree. By scrutinizing the overheads of existing Booth encoding algorithms, the notion of covalent redundant binary Booth encoding was briefly introduced in [19].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A New Redundant Binary Booth Encoding for Fast $2^{n}$-Bit Multiplier Design

Chang

2009

IEEE Trans. Circuits Syst. I

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Section: A Radix-4 Covalent Redundant Binary Booth Encoding (Crbbe-2)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A New Redundant Binary Booth Encoding for Fast $2^{n}$-Bit Multiplier Design

Chang

2009

IEEE Trans. Circuits Syst. I

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“…The additional delay required to add an extra partial product row critically slows down short operand length multiplier due to the relatively fewer number of adder stages in its partial product summing tree. This is the case especially for the power-of-two operand lengths, which are the most commonly encountered word lengths for application-specific data paths and general computing benchmarks [37,38,[71][72][73][74]. Therefore, new RB multiplier architecture with BEPPGs that eradicates the overhead of negation, especially for powerof-two operand lengths, is another perspective that has not been delved into adequately.…”

mentioning

confidence: 99%

Design and analysis of redundant binary booth multipliers

He¹

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First and foremost, I am deeply indebted to my supervisor, Associate Professor Chang Chip Hong, for all of his invaluable guidance, continuous technical and personal support during my PhD candidature at Nanyang Technological University. His many years of research experience and unique sense in engineering research have led to a very effective and insightful guidance to my research work. In particular, I wish to thank him for teaching me the philosophies of research and intangible skills, which are the most important knowledge I have acquired in this research program. What I have learned from him will benefit me well beyond my graduation in my future career and personal life. Special thanks to Mrs. Chang for her continuous concern and kindness, from which I gained lots of wonderful memories. I really treasure the time spent with them. I would like to thank Dr. Gu Jiangmin and Dr. Hossam A. H. Fahmy for their valuable discussions, suggestions and support in the research work. I would also like to thank the fellow members from the Chip's Family for the long run friendship, and invaluable help pertaining to my research. To the staffs and other students in the Center for Integrated Circuits and Systems (CICS) and the Center for High Performance Embedded Systems (CHiPES), I wish to convey my appreciation to all of them for their kind and friendly i ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library ii assistance. ACKNOWLEDGEMENTS I would also like to express my gratitude to my previous supervisors and colleagues in the Institute of Microelectronics (IME). I would not have been here in Singapore if Dr. Xue Ping had not recruited me as a digital Ie designer in 2001. I would like to thank Ms. Doreen Yeo Lee Guek and Mr. Wang Zhongjun particularly for their guidance in the early stage of my career. I am grateful to my fiance Li Qiang for his devotion, understanding, and patience. I would never know whether I am able to go through the tough time without his support. He is the most important source of inspiration, encouragement, and happiness. My parents are always there for me and always have faith in me. It is never enough to say thanks to them. I dedicate this thesis to my parents with all my love.

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A VLSI chip implementation of an A/D converter error table compensator

Cited by 2 publications

References 4 publications

A New Redundant Binary Booth Encoding for Fast $2^{n}$-Bit Multiplier Design

A New Redundant Binary Booth Encoding for Fast $2^{n}$-Bit Multiplier Design

Design and analysis of redundant binary booth multipliers

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