A New Redundant Binary Booth Encoding for Fast $2^{n}$-Bit Multiplier Design

He, Yajuan; Chang, Chip-Hong

doi:10.1109/tcsi.2008.2008503

Cited by 32 publications

(2 citation statements)

References 26 publications

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“…This was extracted to a set of 32-bit strings to analyze any carry skip adder. Another bit string was presented, using the 24000 counter in [10] as the final adder, for a CMOS implementation, which generates a 3 * ( + 1) bit string sequence to analyze an M-bit counter [11]. The operand pattern producer implementation for this method needs an M+1 bit string as providing the best overall computation for carry hybrid adders in general, it does not completely analyze all kinds of designs.…”

Section: Hybrid Additionmentioning

confidence: 99%

A New Partial Product Reduction Algorithm using Modified Counter and Optimized Hybrid Network

Asadi

2015

IJIEEB

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In this paper, a new multiplier is presented which uses modified fourteen transistor adder and optimized hybrid counter for partial product reduction step. Conventional adder is modified to improve Wallace tree functionality. Reducing critical path in counter structure can reduce VLSI area in whole multiplier structure. This paper uses a new structure in partial product reduction step to increase speed. Four to two compressors are used in modified Wallace structure to minimize the critical path. In final addition step of algorithm a new carry lookahead network is presented which adds two final operands efficiently. It uses dynamic CMOS in transistor level to reduce power consumption. Proposed multiplier reduces critical path, increases speed and decreases wiring problems in compare with previous algorithms efficiently. A new Booth encoder is presented in radix 16 circuitry. It decreases number of partial products while hardware overhead is minimized.

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Section: Hybrid Additionmentioning

confidence: 99%

A New Partial Product Reduction Algorithm using Modified Counter and Optimized Hybrid Network

Asadi

2015

IJIEEB

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“…Considering both operation accuracy and hardware complexity, several schemes based on truncation error compensation (TEC) have been presented for fixed-width Baugh-Wooley multipliers [5][6][7][8] or fixed-width Booth multipliers (FWBMs) [9][10][11][12][13][14][15][16][17][18][19][20][21][22]. The Booth multiplier has benefits in achieving high hardware efficiency because the number of rows of partial products is significantly reduced [23,24]. Moreover, the lower level of truncated partial products for Booth multipliers profits the fixed-width operation accuracy [17,18].…”

Section: Introductionmentioning

confidence: 99%

An Accuracy-Improved Fixed-Width Booth Multiplier Enabling Bit-Width Adaptive Truncation Error Compensation

et al. 2021

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Fixed-width Booth multipliers (FWBMs) generate a product with the same bit width as the operand and have been extensively employed in many digital systems. Various truncation error compensation (TEC) schemes have been presented for FWBM designs, aiming to reduce hardware costs while preserving operation accuracy. In general, the existing TEC methods function adequately for an exact bit width of the operand but fail to consider the TEC effect for FWBM inputs with various bit-width levels. To address this issue, we propose a bit-width adaptive TEC (BWATEC) scheme for providing high-accuracy TEC functions that are adaptive to the multiple Lʹ-bit numerical ranges of input data for an L-bit FWBM (Lʹ ≤ L). We also present adjustable architecture for a 16-bit FWBM to enable the proposed BWATEC scheme and evaluate the hardware performance, using the TSMC 40 nm standard cell library. Relative to the contrast 16-bit FWBM approaches that use state-of-the-art TEC methods, the proposed BWATEC-enabled FWBM design can achieve reductions in the area-delay-error product of 7.9%–50.9%, 17.1%–69.5%, 29.9%–82.2%, and 100% for the 14-bit, 12-bit, 10-bit, and 8-bit inputs, respectively. Moreover, the resultant 16-bit FWBM with BWATEC was verified by using the field-programmable gate array for convolutional neural network acceleration.

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Design and Evaluation of Booth-Encoded Multipliers in Redundant Binary Representation

Yang

Chang

2017

Embedded Systems Design With Special Arithmetic and Number Systems

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The state-of-the-art digital signal processing applications play an important role in making the complex real-time algorithms for speech, audio, image processing, video, control and communication systems economically feasible [1][2][3][4]. Multiplication is one of the most commonly used arithmetic operators in these applicationspecific datapaths. Comparing with many other arithmetic operations, multiplication is time consuming and power hungry. The critical paths dominated by digital multipliers often impose speed limits on the entire design. Therefore, there have been an immense volume of publications and endless research interest in the design of energy efficient digital multipliers at different design abstraction levels [5][6][7][8].Most digital multiplier designs are based on the two's complement arithmetic, which is referred to as normal binary (NB) arithmetic as opposed to the redundant binary (RB) arithmetic studied in this chapter. Fast NB multipliers use modified Booth encoders, and 3-to-2 counters or 4-to-2 compressors in a tree structure for parallel computation [9][10][11]. In the last three decades, most speed improvements in this architecture have been achieved via extreme circuit optimization and the use of advanced fabrication technology. The gain resulting from architectural innovation is almost stagnant. It is conjecture that new insight into energy efficient multiplier design is likely to be derived from an alternative arithmetic with a different Y. He ( ) •

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A New Redundant Binary Booth Encoding for Fast $2^{n}$-Bit Multiplier Design

Abstract: A new redundant binary Booth encoding for fast 2^n-bit multiplier design

Cited by 32 publications

References 26 publications

A New Partial Product Reduction Algorithm using Modified Counter and Optimized Hybrid Network

A New Partial Product Reduction Algorithm using Modified Counter and Optimized Hybrid Network

An Accuracy-Improved Fixed-Width Booth Multiplier Enabling Bit-Width Adaptive Truncation Error Compensation

Design and Evaluation of Booth-Encoded Multipliers in Redundant Binary Representation

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