Design and Evaluation of Booth-Encoded Multipliers in Redundant Binary Representation

Abstract

The state-of-the-art digital signal processing applications play an important role in making the complex real-time algorithms for speech, audio, image processing, video, control and communication systems economically feasible [1][2][3][4]. Multiplication is one of the most commonly used arithmetic operators in these applicationspecific datapaths. Comparing with many other arithmetic operations, multiplication is time consuming and power hungry. The critical paths dominated by digital multipliers often impose speed limits on the entire design. Therefore, there have been an immense volume of publications and endless research interest in the design of energy efficient digital multipliers at different design abstraction levels [5][6][7][8].Most digital multiplier designs are based on the two's complement arithmetic, which is referred to as normal binary (NB) arithmetic as opposed to the redundant binary (RB) arithmetic studied in this chapter. Fast NB multipliers use modified Booth encoders, and 3-to-2 counters or 4-to-2 compressors in a tree structure for parallel computation [9][10][11]. In the last three decades, most speed improvements in this architecture have been achieved via extreme circuit optimization and the use of advanced fabrication technology. The gain resulting from architectural innovation is almost stagnant. It is conjecture that new insight into energy efficient multiplier design is likely to be derived from an alternative arithmetic with a different Y. He ( ) •