A VLSI design for a trace-back Viterbi decoder

Time And Energy Efficient Viterbi Decoding Using FPGAs

“…Another drawback is that all the multiplexers and registers are active during the decoding procedure, which consume a lot of power. Hence, while their de- In contrast, using techniques such as the one-bit function proposed in [8], the trace-back algorithm stores the transitions between two consecutive steps on the trellis. No path copying is required when a path is discarded.…”

“…al. [8] propose a fully pipelined VLSI architecture to implement Viterbi decoding using a trace-back algorithm. Their design achieves a high throughput of one output symbol per clock cycle.…”

“…It would also result in high energy dissipation due to significantly high switching activity. Therefore, the design in [8] is not suitable for implementation on FPGAs.…”

“…The path selection results, d k , 0 ≤ k ≤ 2 K−1 − 1, is represented using the one-bit function proposed in [8]. For example, we consider the possible connections between two consecutive steps on the decoding trellis as shown in Figure 2 1, 0, 1).…”

“…Several researchers have implemented Viterbi decoders on FPGAs [6], [8] (See Section 2 for more details). However, these designs either fail to provide high throughput (requiring tens of clock cycles to generate each output symbol) or use a lot of registers and multiplexers and thus consume a lot of energy.…”