A VLSI neural processor for image data compression using self-organization networks

Abstract

An adaptive electronic neural network processor has been developed for high-speed image compression based on a frequency-sensitive self-organization algorithm. The performance of this self-organization network and that of a conventional algorithm for vector quantization are compared. The proposed method is quite efficient and can achieve near-optimal results. The neural network processor includes a pipelined codebook generator and a paralleled vector quantizer, which obtains a time complexity O(1) for each quantization vector. A mixed-signal design technique with analog circuitry to perform neural computation and digital circuitry to process multiple-bit address information are used. A prototype chip for a 25-D adaptive vector quantizer of 64 code words was designed, fabricated, and tested. It occupies a silicon area of 4.6 mmx6.8 mm in a 2.0 mum scalable CMOS technology and provides a computing capability as high as 3.2 billion connections/s. The experimental results for the chip and the winner-take-all circuit test structure are presented.

A low-power CMOS analog vector quantizer

“…The core of the VQ consists of a 16 16 2-D array of distance estimation cells, configured to interconnect columns and rows according to the vector input components and template outputs. Each cell computes in parallel the absolute difference distance between one component of the input vector and the corresponding component of one of the template vectors (1) The MAD distance between input and template vectors is accumulated along rows (2) and presented to the WTA, which selects the single winner (3) All computations in the VQ processor are performed in parallel, including the distance estimations and the winnertake-all search. It is by now well known that parallel architectures allow energetically more efficient implementation in CMOS for a given computational bandwidth requirement.…”

“…The circuit implementation of the WTA function combines the compact sizing and modularity of a linear architecture as in [3], [11], and [12] with positive feedback for fast and decisive output settling independent of signal levels, as in [4] and [5]. Typical positive feedback structures for WTA operation use a logarithmic tree [5] or a fully interconnected network [4], with implementation complexities of order and , respectively, being the number of WTA inputs.…”

“…We note that a similar limitation of dynamic range applies to other distance metrics with vanishing sensitivity near the zero crossover point as well, the popular mean square error (MSE) formulation in particular. The MSE metric is frequently adopted in VQ implementations using strong inversion, squaring MOS circuitry [3], [5]. Due to the relatively wide flat region of the MSE distance function near the origin, it fails to discriminate subtle differences between templates which are more pronounced with a MAD metric.…”

Embedded Analog CMOS Neural Network inside high speed camera

“…On the other hand, the human vision system is very preferment in terms of image analysis which extracts relevant information. In the last few years, technical progresses in signal acquisition [2,3] and processing have allowed the development of new artificial vision system which equals or overpasses human capacities.…”

A parallel processing VLSI BAM engine

“…Melton et al [21] noted that, in a large analog network the large number of analog signals which must pass between chips will exceed the available input-output (I/O) resources, while, the noise and the parasitic capacitances on extended I/O lines will distort operation of the network and possibly lead to erronous results. Also, use of ancillary chips such as D/A and external weight storage [31] adds considerable overhead to system-level implementation. This is a serious limitation of large analog computing networks.…”