1989
DOI: 10.1007/978-1-4613-1619-0_24
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A VLSI Systolic Array Dedicated to Hopfield Neural Network

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Cited by 21 publications
(5 citation statements)
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“…Winner-take-all networks, which utilize recurrent inhibitory connections to force a single output, have also been implemented in neuromorphic systems [1107]- [1109]. Hopfield networks were especially common in earlier neuromorphic implementations, as is consistent with neural network research at that time [5], [6], [13], [15], [759], [764], [813], [1110]- [1148], but there are also more recent implementations [838], [1149]- [1159]. Similarly, associative memory based implementations were also significantly more popular in earlier neuromorphic implementations [1053], [1160]- [1182].…”
Section: Network Modelsmentioning
confidence: 83%
See 1 more Smart Citation
“…Winner-take-all networks, which utilize recurrent inhibitory connections to force a single output, have also been implemented in neuromorphic systems [1107]- [1109]. Hopfield networks were especially common in earlier neuromorphic implementations, as is consistent with neural network research at that time [5], [6], [13], [15], [759], [764], [813], [1110]- [1148], but there are also more recent implementations [838], [1149]- [1159]. Similarly, associative memory based implementations were also significantly more popular in earlier neuromorphic implementations [1053], [1160]- [1182].…”
Section: Network Modelsmentioning
confidence: 83%
“…Full custom or application specific integrated circuit (ASIC) chips have also been very common for neuromorphic implementations [6], [9], [348], [350], [389]- [404], [438], [477], [677], [683], [749]- [764], [764]- [808], [1047], [1048], [1054]- [1060], [1100], [1101], [1118]- [1130], [1170], [1183]- [1185], [1204], [1205], [1212], [1236]- [1242], [1260], [1275], [1283], [1363], [1410], [1527]- [1561]. IBM's TrueNorth, one of the most popular present-day neuromorphic implementations, is a full custom ASIC design [1562]- [1569].…”
Section: A High-levelmentioning
confidence: 99%
“…The first one for FPGA, which has been used frequently in neuromorphic systems [17]. Another one is custom or application-specific integrated circuit (ASIC) chips, which is also common neuromorphic implementations [35].…”
Section: Introductionmentioning
confidence: 99%
“…Finally, for neurochips and neurocomputers which are dedicated to a certain neural architecture (e.g., the Boltzmann machine (Murray et al 1992(Murray et al , 1994; Kohonen's self-organizing feature maps (Hochet et al C1.4, C2.1.1 1991, Goser et al 1989, Rüping and Rückert 1996, Tryba et al 1990, Thiran 1993, Thiran et al 1994, Thole et al 1993; Hopfield networks (Blayo and Hurat 1989, Gascuel et al 1992, Graf and de Vegvar C1.3.4 1987a, b, Graf et al 1987, Savran and Morgül 1991, Sivilotti et al 1986, Weinfeld 1989, Yasunaga et al 1989; Neocognitron (Trotin andDarbel 1993, White andElmasry 1992); radial basis functions and C2.1.3, C1.6.2 restricted coulomb energy (LeBouquin 1994, Scofield and Reilly 1991)), or for those which are built as C1.6.3.1 stochastic devices (Clarkson and Ng 1993, Clarkson et al 1993a, b, Köllmann et al 1966, it is almost C1.4 impossible to assess their speed. It should be mentioned that due to such unsurmountable problems there is usually little if any information on benchmarks.…”
Section: Beiu Et Almentioning
confidence: 99%
“…Although the system performs lower than CNAPS (described below), we have to mention that SNAP uses 32-bit floating point arithmetic. • The APLYSIE chip is a two-dimensional systolic array dedicated for Hopfield-type networks (Blayo and Hurat 1989). Since the outputs are only +1 and −1, the synaptic multiplication can be performed by an adder/subtracter (like in Weinfeld's 1989 solution).…”
mentioning
confidence: 99%