A Vortex Transitional NDRO Josephson Memory Cell

Tahara, S.; Wada, Y.

doi:10.1143/jjap.26.1463

Cited by 15 publications

(5 citation statements)

References 6 publications

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“…6 mark amplitudes of the IX and IY currents at successful operation cycles of the tested cells, while green crosses mark incorrect operation. The measured margins are similar to the ones projected in [5], demonstrating that performance of the fabricated circuits is in a good agreement with the theoretical model. We attribute wider margins of the VT2 cells in comparison to the ones observed on VT1 cells to a better layout optimization and parameter extraction, mainly to a better account for the mutual inductances between all the cell inductors, including parasitics -the experience gained as a result of our work on the VT1 cells.…”

Section: Circuit Design and Test Resultssupporting

confidence: 80%

“…Unfortunately, it has not been complemented by a similar revolution in JJ-based random access memories (RAM). The development of superconductor RAMs slowed down after the demonstration of a Vortex Transitional (VT) memory cell [5], [6] and VT-based RAM circuits in 1990s [7], [8]. The 4-Kbit level of RAM integration achieved at that time was in line with available fabrication technologies.…”

Section: Introductionmentioning

confidence: 99%

“…Cumulative margins of 70 cells in the 12 x 6 array are shown. Cells(5,2) and(5,6) failed and were excluded from the test.…”

mentioning

confidence: 99%

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Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories

Семенов

Polyakov

Tolpygo

2019

IEEE Trans. Appl. Supercond.

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Arrays of Vortex Transitional (VT) memory cells with functional density up to 1 Mbit/cm 2 have been designed, fabricated, and successfully demonstrated. This progress is due to recent advances in design optimization and in superconductor electronics fabrication achieved at MIT Lincoln Laboratory.As a starting point, we developed a demo array of VT cells for the 100-μA/μm 2 MIT LL fabrication process SFQ5ee with 8 niobium layers. The studied two-junction memory cell with a twojunction nondestructive readout occupied 168 μm 2 , resulting in an over 0.5 Mbit/cm 2 functional density. Then, we reduced the cell area down to 99 μm 2 (corresponding to over 0.9 Mbit/cm 2 functional density) by utilizing self-shunted Josephson Junctions (JJs) with critical current density, Jc of 600 µA/μm 2 and eliminating shunt resistors. The fabricated high-Jc memory cells were fully operational and possessed wide Read/Write current margins, quite close to the theoretically predicted values. We discuss approaches to further increasing the integration scale of superconductor memory and logic circuits: a) miniaturization of superconducting transformers by using soft magnetic materials; b) reduction of JJ area by using planar high-Jc junctions similar to variable thickness bridges.

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Section: Circuit Design and Test Resultssupporting

confidence: 80%

Section: Introductionmentioning

confidence: 99%

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Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories

Семенов

Polyakov

Tolpygo

2019

IEEE Trans. Appl. Supercond.

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“…In CMOS design, it is common to use the RAM-based cache. Although, in SFQ design, there are some RAM-based memory technologies such as Vortex Transition Cell (or VTC) [35], they are not fast enough to provide data to microprocessors which operate over 100 GHz. Therefore, shift-register-based memory technology is employed to achieve more fast access speed.…”

Section: Bit-parallel Sfq Cache Architecturementioning

confidence: 99%

Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing

Ishida

Tanaka

Ono

et al. 2018

IEICE Trans. Electron.

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SUMMARYCMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and onchip cache architectures.

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“…Vortex-based memory has also shown promising results in terms of its scalability. Tahara et al [19] demonstrated vortex-based NDRO in one of the earliest accounts of this memory. Numata et al [20] demonstrated a high-density memory application with a relatively lower area.…”

Section: Introductionmentioning

confidence: 98%

Development of an Optimizer for Vortex Transitional Memory Using Particle Swarm Optimization

Karamuftuoglu

Demirhan

Komura

et al. 2016

IEEE Trans. Appl. Supercond.

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Superconductor electronics (SCE) is a promising complementary and beyond CMOS technology. However, despite its practical benefits, the realization of SCE logic faces a significant challenge due to the absence of dense and scalable nonvolatile memory designs. While various nonvolatile memory technologies, including Non-destructive readout, vortex transitional memory (VTM), and magnetic memory, have been explored, achieving a superconductor random-access memory (RAM) crossbar array remains challenging. This paper introduces a novel, nonvolatile, high-density, and scalable VTM cell design for SCE applications. Our proposed design addresses scaling issues while boasting zero static power consumption characteristics. Our design leverages current summation, enabling analog multiply-accumulate operations -an essential feature for many in-memory computational tasks. We demonstrate the efficacy of our approach with a 32×32 superconductor memory array operating at 20 GHz. This design effectively addresses scaling issues and utilizes current summation that can be used for analog multiply-accumulate operations. Additionally, we showcase the accumulation property of the memory through analog simulations conducted on an 8×8 superconductor crossbar array.

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A Vortex Transitional NDRO Josephson Memory Cell

Cited by 15 publications

References 6 publications

Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories

Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories

Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing

Development of an Optimizer for Vortex Transitional Memory Using Particle Swarm Optimization

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