A wear-leveling-aware dynamic stack for PCM memory in embedded systems

Li, Qingan; Yanxiang, He; Chen, Yong; Jiang, Nan; Xu, Chao

doi:10.7873/date.2014.102

Cited by 6 publications

(4 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These efforts are orthogonal to our research on writes reduction of non-volatile main memory allocator. At software level, a sea of optimize techniques have been proposed to minimize the total number of memory writes to PCM in terms of program variables, application access patterns [14][15][16][17][18][19]. Access patterns of embedded systems' applications are fixed such that facilitate optimization at compilation level.…”

Section: Discussionmentioning

confidence: 99%

WAlloc: An efficient wear-aware allocator for non-volatile main memory

Xiao

Deng

et al. 2015

2015 IEEE 34th International Performance Computing and Communications Conference (IPCCC)

View full text Add to dashboard Cite

The non-volatile memory NVM has the illustrious merits of byte-addressability, fast speed, persistency and low power consumption, which make it attractive to be used as main memory. Commonly, user process dynamically acquires memory through memory allocators. However, traditional memory allocators designed with in-place data writes are not appropriate for non-volatile main memory NVRAM due to the limited endurance. For instance, the number of write operations is merely 10 8 times per PCM cell. In this paper, we quantitatively analyze the wear-oblivious of DRAM-oriented designed allocator-glibc malloc and the inefficiency of wearconscious allocator-NVMalloc. For example, the average imbalance factor (the maximum/the average) of memory allocation is about 7.5 and 3, respectively. Based on our observations, we propose WAlloc, an efficient wear-aware manual memory allocator designed for NVRAM, decouples metadata and data, uses Less Allocated First Out allocation policy and redirects the data writes. Experimental results show that the wear-leveling of WAlloc outperforms that of NVMalloc about 30% and 60% under random workloads and welldistributed workloads, respectively. In addition, considering the trade-off between space and wear-leveling, WAlloc reduces average data memory writes in 64 bytes block by average 1.5X comparing with malloc with almost 8% extra space overhead. Keywords-Non-Volatile Memory memory allocator wearaware I.978-1-4673-8590-9/15/$31.00 ©2015 IEEE

show abstract

Section: Discussionmentioning

confidence: 99%

WAlloc: An efficient wear-aware allocator for non-volatile main memory

Xiao

Deng

et al. 2015

2015 IEEE 34th International Performance Computing and Communications Conference (IPCCC)

View full text Add to dashboard Cite

show abstract

“…As long as generic mechanisms (e.g., virtual memory page remapping) are used [1,2], the modifications to the algorithms are minimal. In contrast, when specific mechanisms (e.g., heap allocation or stack allocation) are used for wear-leveling [14,15,20], then read wear-leveling cannot be integrated easily. Thus, another special mechanism for read wear-leveling is required in those cases.…”

Section: Read Wear-levelingmentioning

confidence: 99%

Software-Managed Read and Write Wear-Leveling for Non-Volatile Main Memory

Hakert

Chen

Schirmeier

et al. 2022

ACM Trans. Embed. Comput. Syst.

View full text Add to dashboard Cite

In-memory wear-leveling has become an important research field for emerging non-volatile main memories over the past years. Many approaches in the literature perform wear-leveling by making use of special hardware. Since most non-volatile memories only wear out from write accesses, the proposed approaches in the literature also usually try to spread write accesses widely over the entire memory space. Some non-volatile memories, however, also wear out from read accesses, because every read causes a consecutive write access. Software-based solutions only operate from the application or kernel level, where read and write accesses are realized with different instructions and semantics. Therefore different mechanisms are required to handle reads and writes on the software level. First, we design a method to approximate read and write accesses to the memory to allow aging aware coarse-grained wear-leveling in the absence of special hardware, providing the age information. Second, we provide specific solutions to resolve access hot-spots within the compiled program code (text segment) and on the application stack. In our evaluation, we estimate the cell age by counting the total amount of accesses per cell. The results show that employing all our methods improves the memory lifetime by up to a factor of 955×.

show abstract

“…Considering an environment without an MMU, such as a low-end MCU, some studies have attempted wear leveling of the stack through a software technique. Dynamic stack [28] distributes writes to the stack by adjusting the position of the stack frame to account for wear. However, writes occurring inside the stack frame are not considered.…”

Section: Related Workmentioning

confidence: 99%

Improving NVM Lifetime Using Task Stack Migration on Low-End MCU-Based Devices

et al. 2022

View full text Add to dashboard Cite

Tiny embedded devices are cost and energy-sensitive, and high-density emerging non-volatile memory (NVM) can help reduce energy consumption at a fraction of the cost. However, high-density NVM has low write endurance compared to volatile memory, so it is vulnerable to write concentration. Most NVM lifetime improvement studies in the existing embedded environment have distributed writes by modifying the mapping relationship between physical and logical addresses. However, applying the existing wear leveling techniques in low-end MCUs such as ARM Cortex M3/M4 that use only physical addresses is hard. Therefore, we wear-level the write-heavy stack area to improve the NVM lifetime in low-end MCUs. However, since the stack of bare metal applications is difficult to move during runtime, we implement the migration function targeting the task stack of FreeRTOS. The task stack moves based on time, and to avoid the pointer validation problem caused by the movement of the task stack, we migrate the stack under safe conditions. In addition, FreeRTOS uses a single heap to preferentially allocate to low free space, which reduces the degree of freedom where the stack moves, reducing the effect of distributing the writes. To alleviate this problem, we add another heap for the stack migration and introduce circular dynamic allocation in the heap. Through our experiments, the proposed method was about 19.6% larger than the ideal case of maximum write, and the computational overhead was about 0.2%. INDEX TERMSEmbedded software, Memory management, Nonvolatile memory, Real-time systems I. INTRODUCTION Emerging non-volatile memory (NVM) is capable of random access, consumes low standby power, and has a performance close to that of volatile memory, so it can simultaneously serve as the main memory and storage of a tiny embedded device. When ultra-compact embedded devices reduce energy consumption by using NVM [1], applications such as TinyML [2]-[4] that perform data acquisition and machine learning simultaneously can run for a long time by placing the device close to the data. NVM can be divided into lowdensity NVM and high-density NVM. High-density NVMs such as phase-change memory (PCM) [5] or multi-level cell (MLC) spin transfer torque magnetoresistive random-access memory (STT-MRAM) [6], [7] have lower performance and shorter lifetime than low-density NVMs such as a singlelevel cell(SLC) STT-MRAM [8], [9], but high-density NVMs are cheaper based on the same memory capacity.Although computing performance and energy consumption characteristics are essential for tiny embedded devices, the device's manufacturing cost is also important. In other words, using a high-density NVM in a tiny embedded device means that the tiny embedded device can be manufactured at a relatively

show abstract

A wear-leveling-aware dynamic stack for PCM memory in embedded systems

Cited by 6 publications

References 0 publications

WAlloc: An efficient wear-aware allocator for non-volatile main memory

WAlloc: An efficient wear-aware allocator for non-volatile main memory

Software-Managed Read and Write Wear-Leveling for Non-Volatile Main Memory

Improving NVM Lifetime Using Task Stack Migration on Low-End MCU-Based Devices

Contact Info

Product

Resources

About