WAlloc: An efficient wear-aware allocator for non-volatile main memory

Yu, Songping; Xiao, Nong; Deng, Mingzhu; Xing, Yuxuan; Liu, Fang; Cai, Zhiping; Chen, Wei

doi:10.1109/pccc.2015.7410326

Cited by 20 publications

(12 citation statements)

References 35 publications

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“…Both approaches are often combined to achieve a randomized wear-leveling on fine granularities inside of memory blocks, whereas an aging-aware approach is used to target these coarse-grained memory blocks. The granularity also varies from single bits [3,23] over cache-lines [19,24] for fine-grained approaches to memory pages [1,2,5,6,20] or even bigger memory segments [22,24] for coarse-grained approaches. Some approaches are not based on remapping the physical memory content through an abstraction layer, but hook into the memory allocation process of the operating system to apply wear-leveling to the memory allocator [1,15,20].…”

Section: Related Workmentioning

confidence: 99%

“…The granularity also varies from single bits [3,23] over cache-lines [19,24] for fine-grained approaches to memory pages [1,2,5,6,20] or even bigger memory segments [22,24] for coarse-grained approaches. Some approaches are not based on remapping the physical memory content through an abstraction layer, but hook into the memory allocation process of the operating system to apply wear-leveling to the memory allocator [1,15,20]. Li et al [15] also propose to use an allocated memory portion, whenever a function is called, for the function's stack memory to wear-level the stack region.…”

Section: Related Workmentioning

confidence: 99%

“…As long as generic mechanisms (e.g., virtual memory page remapping) are used [1,2], the modifications to the algorithms are minimal. In contrast, when specific mechanisms (e.g., heap allocation or stack allocation) are used for wear-leveling [14,15,20], then read wear-leveling cannot be integrated easily. Thus, another special mechanism for read wear-leveling is required in those cases.…”

Section: Read Wear-levelingmentioning

confidence: 99%

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Software-Managed Read and Write Wear-Leveling for Non-Volatile Main Memory

Hakert

Chen

Schirmeier

et al. 2022

ACM Trans. Embed. Comput. Syst.

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In-memory wear-leveling has become an important research field for emerging non-volatile main memories over the past years. Many approaches in the literature perform wear-leveling by making use of special hardware. Since most non-volatile memories only wear out from write accesses, the proposed approaches in the literature also usually try to spread write accesses widely over the entire memory space. Some non-volatile memories, however, also wear out from read accesses, because every read causes a consecutive write access. Software-based solutions only operate from the application or kernel level, where read and write accesses are realized with different instructions and semantics. Therefore different mechanisms are required to handle reads and writes on the software level. First, we design a method to approximate read and write accesses to the memory to allow aging aware coarse-grained wear-leveling in the absence of special hardware, providing the age information. Second, we provide specific solutions to resolve access hot-spots within the compiled program code (text segment) and on the application stack. In our evaluation, we estimate the cell age by counting the total amount of accesses per cell. The results show that employing all our methods improves the memory lifetime by up to a factor of 955×.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Read Wear-levelingmentioning

confidence: 99%

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Software-Managed Read and Write Wear-Leveling for Non-Volatile Main Memory

Hakert

Chen

Schirmeier

et al. 2022

ACM Trans. Embed. Comput. Syst.

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“…The authors propose to extend CPU caches with line counters to track which lines have been flushed. Yu et al [30] proposed WAlloc, a persistent memory allocator optimized for wear leveling. In contrast to NVMalloc and WAlloc, we focus on performance and defragmentation, and ignore wear-leveling which we envision will be addressed at the hardware level.…”

Section: Related Workmentioning

confidence: 99%

Memory management techniques for large-scale persistent-main-memory systems

Oukid

Booss

Lespinasse³

et al. 2017

Proc. VLDB Endow.

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Storage Class Memory (SCM) is a novel class of memory technologies that promise to revolutionize database architectures. SCM is byte-addressable and exhibits latencies similar to those of DRAM, while being non-volatile. Hence, SCM could replace both main memory and storage, enabling a novel single-level database architecture without the traditional I/O bottleneck. Fail-safe persistent SCM allocation can be considered conditio sine qua non for enabling this novel architecture paradigm for database management systems. In this paper we present PAllocator, a fail-safe persistent SCM allocator whose design emphasizes high concurrency and capacity scalability. Contrary to previous works, PAllocator thoroughly addresses the important challenge of persistent memory fragmentation by implementing an efficient defragmentation algorithm. We show that PAllocator outperforms state-of-the-art persistent allocators by up to one order of magnitude, both in operation throughput and recovery time, and enables up to 2.39x higher operation throughput on a persistent B-Tree.

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“…Accordingly, the problem has been tackled in the literature and several in-memory wear-leveling techniques have been proposed. A majority of these techniques is agingaware [3], [8], [11], [13], [14], [16], [18], [19], [22], [26], which means that the current cell age or the current write count is taken into account for the wear-leveling decisions. The wearleveling itself is mostly realized through an abstraction layer, which remaps the physical location of logical memory regions.…”

Section: Introductionmentioning

confidence: 99%

SoftWear: Software-Only In-Memory Wear-Leveling for Non-Volatile Main Memory

Hakert,

Chen,

Genssler

et al. 2020

Preprint

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Several emerging technologies for byte-addressable non-volatile memory (NVM) have been considered to replace DRAM as the main memory in computer systems during the last years. The disadvantage of a lower write endurance, compared to DRAM, of NVM technologies like Phase-Change Memory (PCM) or Ferroelectric RAM (FeRAM) has been addressed in the literature. As a solution, in-memory wear-leveling techniques have been proposed, which aim to balance the wear-level over all memory cells to achieve an increased memory lifetime. Generally, to apply such advanced aging-aware wear-leveling techniques proposed in the literature, additional special hardware is introduced into the memory system to provide the necessary information about the cell age and thus enable aging-aware wearleveling decisions.This paper proposes software-only aging-aware wear-leveling based on common CPU features and does not rely on any additional hardware support from the memory subsystem. Specifically, we exploit the memory management unit (MMU), performance counters, and interrupts to approximate the memory write counts as an aging indicator. Although the software-only approach may lead to slightly worse wear-leveling, it is applicable on commonly available hardware. We achieve page-level coarsegrained wear-leveling by approximating the current cell age through statistical sampling and performing physical memory remapping through the MMU. This method results in nonuniform memory usage patterns within a memory page. Hence, we further propose a fine-grained wear-leveling in the stack region of C / C++ compiled software.By applying both wear-leveling techniques, we achieve up to 78.43% of the ideal memory lifetime, which is a lifetime improvement of more than a factor of 900 compared to the lifetime without any wear-leveling.

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WAlloc: An efficient wear-aware allocator for non-volatile main memory

Cited by 20 publications

References 35 publications

Software-Managed Read and Write Wear-Leveling for Non-Volatile Main Memory

Software-Managed Read and Write Wear-Leveling for Non-Volatile Main Memory

Memory management techniques for large-scale persistent-main-memory systems

SoftWear: Software-Only In-Memory Wear-Leveling for Non-Volatile Main Memory

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