A Wide Band CDR for Digital Video Data Transmission

Ozawa, Shouhei; Miura, S.; Kousokabe, S.; Ishizone, Yohei; Tomosugi, S.; Okamura, J.

doi:10.1109/asscc.2005.251782

Cited by 5 publications

(1 citation statement)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The embedded clock scheme is used in a serial link for optical communication [4]. It is also utilized in the Bus LVDS SerDes transceiver and the system interface for the FPD system [5,6]. However, these serial links adopt a sophisticated phaselocked loop (PLL)-based clock recovery scheme which is not suitable for the column driver because it is difficult to design and implement the PLL-based clock recovery circuit.…”

Section: Introductionmentioning

confidence: 99%

64.5L: Late‐News Paper: A Clock Embedded Differential Signaling (CEDS™) for the Next Generation TFT‐LCD Applications

Jeon

Moon

Seo

et al. 2009

Symp Digest of Tech Papers

View full text Add to dashboard Cite

A CEDS™ (Clock Embedded Differential Signaling) interface for the next generation TFT‐LCD applications is proposed. The proposed intra‐panel interface reduces the number of signal lines in the TFT‐LCD panel by embedding the clock signal in transmitted data without explicit clock lines, and it provides low EMI, low power consumption and high data rate. The CEDS protocol provides an embedded clock recovery scheme which is based on the delay‐locked loop (DLL). The CEDS interface is verified on a 42‐inch full‐HD (1920×1080) TFT‐LCD panel with the 10‐bit RGB and 120Hz driving technology. The maximum data rate is measured as higher than 1.405Gb/s, with a pixel clock frequency of up to 330MHz.

show abstract

Section: Introductionmentioning

confidence: 99%