A wide-band tuning system for fully integrated satellite receivers

Vaucher, C.S.; Kasperkovitz, D.

doi:10.1109/4.701238

Cited by 65 publications

(30 citation statements)

References 12 publications

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“…Standard FM modulation theory and the small angle approximation lead to the following equation for the amplitude of the spurious signal (in dBc), which is at an offset frequency from the carrier: spurious (5) where offset frequency from the carrier (Hz); amplitude of ac current component with frequency (A); impedance of the loop filter at (V/A); VCO gain (Hz/V). The value of is twice the value of the loop-filter dc leakage current [12] in loops operating with well-designed charge pumps. In cases where the charge pump has chargesharing problems and/or charge injection into the loop filter, may become dominated by these second-order effects.…”

Section: Reference Spurious Signals and Loop Filter Attenuationmentioning

confidence: 99%

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An adaptive PLL tuning system architecture combining high spectral purity and fast settling time

Vaucher

2000

IEEE J. Solid-State Circuits

106

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Abstract-An adaptive phase-locked loop (PLL) architecture for high-performance tuning systems is described. The architecture combines contradictory requirements posed by different performance aspects. Adaptation of loop parameters occurs continuously, without switching of loop filter components, and without interaction from outside of the tuning system. The relationship of performance aspects (settling time, phase noise, and spurious signals) to design variables (loop bandwidth, phase margin, and loop filter attenuation at the reference frequency) are presented, and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL, optimized for use in a multiband (global) car-radio tuner IC, is described in detail. The realized tuning system achieved state-of-the-art settling time and spectral purity performance in its class (integer-PLL's): a signal-tonoise ratio of 65 dB, a 100-kHz spurious reference breakthrough signal under 81 dBc, and a residual settling error of 3 kHz after 1 ms, for a 20-MHz frequency step. It simultaneously fulfills the speed requirements for inaudible frequency hopping and the heavy signal-to-noise ratio specification of 64 dB.

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Section: Reference Spurious Signals and Loop Filter Attenuationmentioning

confidence: 99%

“…16. The high-frequency part of the programmable divider is based on the programmable prescaler concept described in [12] and consists of a chain of 2/3 divider cells. The modular architecture enables easy optimization of power dissipation and robustness for process variations.…”

Section: A Programmable Dividersmentioning

confidence: 99%

An adaptive PLL tuning system architecture combining high spectral purity and fast settling time

Vaucher

2000

IEEE J. Solid-State Circuits

106

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“…T~is translates to a £(10kHz) for the RO ranging from -85 dBc/Hz to -95 dBc/Hz, dependmg on the integrated ring oscillator phase noise level, the symbol rate of the satellite system and the loop bandwidth of the clock recovery of the QPSK demodulation back-end [38]. The tuning range in Table 9.3 follows from the chosen double-loop architecture.…”

Section: Specificationsmentioning

confidence: 99%

“…In addition, the LO and the tuning system should be constructed in such a way that LO self-reception [150] is minimized, which is caused by LO leakage [90] to the antenna. A fundamental solution to the abovementioned problems is the double-loop architecture shown in Figure 9.13 [3,38]. In this tuning system a fully integrated ring oscillator provides the required l/Q signals in the satellite frequency band [229].…”

Section: A 09-22 Ghz Two-integrator Oscillator For Satellite Receiversmentioning

confidence: 99%

“…Both oscillators are part of a double-loop tuning-system for this satellite receiver. The double-loop tuningsystem combines the quadrature property of a two-integrator oscillator with the lowphase-noise property of an LC oscillator [38]. Pulling of the LO and self-reception in the zero-IF architecture of the satellite receiver are minimized, as the two-integrator oscillator is fully integrated and inductorless.…”

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confidence: 99%

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