An adaptive PLL tuning system architecture combining high spectral purity and fast settling time

Vaucher, C.S.

doi:10.1109/4.839909

Cited by 106 publications

(70 citation statements)

References 12 publications

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“…Meanwhile, the loop damping factor should be maintained for preserving the loop dynamics and stability. The improvement in locking speed is determined by the expanding ratio of the loop bandwidth, which is often limited by practical implementation considerations [2].…”

Section: ⅰ Introductionmentioning

confidence: 99%

“…Consequently, this approach often requires complex calibrations to realize such a lookup table [5]. Bandwidth switching is another useful technique for decreasing the settling time [2]～ [4]. The main idea of this approach is to widen the loop bandwidth during locking and then change the bandwidth to the desired narrow one when the loop reaches a locked state.…”

Section: ⅰ Introductionmentioning

confidence: 99%

“…To address this trade-off between settling time and loop bandwidth, several works were introduced [2]～ [6]. One design approach is to utilize a pre-determined lookup table to adjust the output frequency immediately [5], [6].…”

Section: ⅰ Introductionmentioning

confidence: 99%

“…In the fast-lock mode, the PLL IC supplies charge pump current * K j [mA/ rad] and the equivalent resistor ( eq R ) of the loop filter is 2 2 ' || R R . Since 2 R¢ is generally small compared to 2 R , the equivalent resistance is approximately equal to 2 R¢ . Due to small 2 R¢ , 2 C is charged faster, which results in a faster lock-time.…”

mentioning

confidence: 99%

“…Since 2 R¢ is generally small compared to 2 R , the equivalent resistance is approximately equal to 2 R¢ . Due to small 2 R¢ , 2 C is charged faster, which results in a faster lock-time. In contrast, the PLL IC supplies a small charge pump current K j [mA/rad] in the normal mode, and the loop filter resistor value is 2 R .…”

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confidence: 99%

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A Lock-Time Improvement for an X-Band Frequency Synthesizer Using an Active Fast-Lock Loop Filter

Heo¹,

Oh²,

Jeong³

et al. 2011

Journal of electromagnetic engineering and science

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In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 μsec and reference spur suppression below -64 dBc. Ⅰ. IntroductionA frequency synthesizer is frequently used as a signal source, and is regarded as an essential device in communication systems. Its frequency can be synthesized using the control signals from a program in a personal computer. Various implementations for frequency synthesizers are proposed [1]. One of them is using PLL (Phase Locked Loop), which is based on frequency divider. Fig. 1 shows a typical block diagram of our frequency synthesizer using frequency dividers. In comparison to a conventional frequency synthesizer, a divider of 1/4 is internally built in a voltage controlled oscillator (VCO) IC. In Fig. 1, a desired where N is division ratio of VCO frequency. Thus, the frequency of VCO can be synthesized with a step frequency CH f by changing the value of N. The important figures of merit in this type of frequency synthesizer are lock-time and reference spur suppression, which are critically dependent on the loop filter bandwidth. As a loop bandwidth increases, lock-time is decreased but spurs increase. Conversely, when a loop bandwidth decreases, spurs are suppressed but lock-time increases.Such trade-off makes it difficult to implement the loop filter to yield both a satisfactory fast lock-time and spur suppression. However, recent communication and military applications require more stringent spectral purity of signal sources, with faster settling time.To address this trade-off between settling time and loop bandwidth, several works were introduced [2]～ [6]. One design approach is to utilize a pre-determined lookup table to adjust the output frequency immediately [5], [6]. The lookup table initially records the proper frequency-setting configurations for all channels. When the PLL is commanded to change its frequency to a certain

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Section: ⅰ Introductionmentioning

confidence: 99%

Section: ⅰ Introductionmentioning

confidence: 99%

Section: ⅰ Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

See 3 more Smart Citations

A Lock-Time Improvement for an X-Band Frequency Synthesizer Using an Active Fast-Lock Loop Filter

Heo¹,

Oh²,

Jeong³

et al. 2011

Journal of electromagnetic engineering and science

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A fast settling frequency synthesizer with switched‐bandwidth loop filter

Beiraghdar

Rad

Sheikhaei

et al. 2021

Circuit Theory & Apps

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SummaryThis paper presents a new method to substantially decrease the settling time of analog phase‐locked loops (PLLs) while keeping its phase noise unaffected. This is achieved by switching the loop filter capacitors and resistor in such a way that output frequency is kept seamless. This method only affects the loop filter architecture and does not need any other changes to other blocks of the PLL. A frequency synthesizer circuit is implemented to validate the proposed method. The reference synthesizer has a 342‐μs settling time for a 1‐GHz frequency step (1.5 to 2.5 GHz), while if the proposed technique is enabled, the settling time is reduced to 48 μs (worst case). The measured phase noise of the synthesizer at 10‐kHz offset from a 2‐GHz carrier is −110 dBc/Hz.

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On the simulation of fast settling charge pump PLLs up to fourth order

Guermandi

Franchi

Gnudi

2011

Circuit Theory & Apps

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SUMMARYIn this paper, we discuss three different models for the simulation of integer-N charge-pump phase-locked loops (PLLs), namely the continuous-time s-domain and discrete time z-domain approximations and the exact semi-analytical time-domain model. The limitations of the two approximated models are analyzed in terms of error in the computed settling time as a function of loop parameters, deriving practical conditions under which the different models are reliable for fast settling PLLs up to fourth order. Besides, output spectral purity analysis methods based upon the time-domain model are introduced and the results are compared with those obtained by means of the s-domain model in terms of phase noise and reference spur estimation. As a case study, we use the three models to analyze a fast switching PLL to be integrated in a frequency synthesizer for WiMedia MB-OFDM UWB systems.

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An adaptive PLL tuning system architecture combining high spectral purity and fast settling time

Cited by 106 publications

References 12 publications

A Lock-Time Improvement for an X-Band Frequency Synthesizer Using an Active Fast-Lock Loop Filter

A Lock-Time Improvement for an X-Band Frequency Synthesizer Using an Active Fast-Lock Loop Filter

A fast settling frequency synthesizer with switched‐bandwidth loop filter

On the simulation of fast settling charge pump PLLs up to fourth order

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