A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology

Chung, Ching-Che; Sheng, Duo; Shen, Sung-En

doi:10.1587/elex.8.1245

Cited by 3 publications

(1 citation statement)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To eliminate the clock duty-cycle errors in memory interface channels, input clock buffers, and on-chip clock trees, typical high-speed DRAM and memory controllers utilize analog-type, digital-type or hybrid-type duty-cycle corrector (DCC) circuits [1,2,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20]. The DCCs in DDR3, DDR4, LPDDR4, LPDDR5, and GDDR5 SDRAM applications performs duty-cycle error compensation of high-speed signal pins for a differential clock (CK/CKb), data signals (DQs), and a data strobe signal (DQS).…”

Section: Introductionmentioning

confidence: 99%

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

Hwang

Kim

2019

IEICE Electron. Express

View full text Add to dashboard Cite

This Letter presents a 0.8-3.4 GHz process variation insensitive full-swing duty-cycle corrector (DCC) for high-speed memory I/O links. The proposed DCC utilizes a new full-swing duty cycle adjuster (DCA) that can provide a full-swing output clock of 50% duty-cycle without using a small-swing to full-swing level shifter. The proposed full-swing DCA is based on a new pseudo-differential feedback delay element (PFDE) and fundamentally eliminates the problem of increased duty-cycle errors due to the use of a level shifter that is vulnerable to process corner variation. The proposed DCC is implemented in a 40-nm CMOS process and achieves an operating frequency range of 0.8-3.4 GHz. The duty-cycle correction range is ²15% at 3.4 GHz. The DCC dissipates 2.8 mW from a 1.0 V supply at 3.4 GHz and occupies an active area of only 0.0054 mm 2 .

show abstract

Section: Introductionmentioning

confidence: 99%

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

Hwang

Kim

2019

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

A 2–8-GHz adaptive duty-cycle corrector loop with background calibration

Kim

Lee

2017

International Journal of Electronics

View full text Add to dashboard Cite

A fast-locking low-jitter pulsewidth control loop for high-speed pipelined ADC

Wang¹,

Zhu²,

Yu³

et al. 2012

IEICE Electron. Express

View full text Add to dashboard Cite

Abstract:A fast-locking, high-precision and low-jitter pulsewidth control loop for high-speed pipelined ADC is presented. Only through controlling the delay of rising edge to adjust duty cycle, the clock jitter could be suppressed greatly. An improved charge pump with a follower circuit and self-biased loop was designed to decrease the voltage ripples for higher accuracy and lower jitter. A start-up circuit was adopted to enable the pulsewidth control loop (PWCL) lock rapidly. Using SMIC 0.18 µm 3.3 V CMOS Spice process model, the simulation results show that within 180 ns the PWCL can lock the clock duty cycles for the accuracy of 50 ± 1% with 10%∼90% input duty cycle from 50 MHz to 250 MHz. The rms-jitter is 73 fs at 250 MHz. Keywords: pipelined ADC, PWCL, fast-locking, low-jitter Classification: Integrated circuits References

show abstract

A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology

Cited by 3 publications

References 11 publications

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

A 2–8-GHz adaptive duty-cycle corrector loop with background calibration

A fast-locking low-jitter pulsewidth control loop for high-speed pipelined ADC

Contact Info

Product

Resources

About