A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS

Lee, Ivan; Tsai, Yun-Ta; Liu, Shen-Iuan

doi:10.1109/tvlsi.2012.2186990

Cited by 9 publications

(8 citation statements)

References 10 publications

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“…It is straightforward from this expression (see Figure 5) and the NCO expression in (7) to see that the 2 nd order joint PLL loop filter plus NCO operation can be written using a state-space formulation as…”

Section: A Conventional Pll Vs Standard Kfmentioning

confidence: 99%

“…Digital PLLs can be implemented in hardware (usually with mixed signal or all-digital integrated circuits in CMOS technology [5]- [7], and targeting frequencies on the order of GHz and above [8]), but the rapid evolution of programmable devices such as field programmable gate arrays (FPGAs), digital signal processors (DSPs), microcontrollers and general purpose processors (GPPs) enables softwaredefined implementations targeting frequencies up to the hundreds of MHz, in which the designer trades electronic components for computation resources [9], [10]. This approach provides advantages such as easy customization of the feedback loop and a drastic reduction in the development cost when compared to the hardware counterpart.…”

mentioning

confidence: 99%

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Are PLLs dead? A tutorial on kalman filter-based techniques for digital carrier synchronization

Vilà‐Valls

Closas

Navarro

et al. 2017

IEEE Aerosp. Electron. Syst. Mag.

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Carrier synchronization is a fundamental stage in the receiver side of any communication or positioning system. Traditional carrier phase tracking techniques are based on well-known phase-locked loop (PLL) closed-loop architectures, which are still the methods of choice in modern receivers. Those techniques are well understood, easy to tune and perform well under benign propagation conditions, but their applicability is seriously compromised in harsh propagation environments where the signal may be affected by high dynamics, shadowing, strong fadings, multipath effects or ionospheric scintillation.From an optimal filtering standpoint, the Kalman filter (KF) is clearly a powerful alternative, but the synchronization community seems still reluctant to exploit all the potential it has to offer. The purpose of this paper is twofold: i) to review the basics and state-of-the-art on both PLL and KF-based tracking techniques, and ii) to present and justify the reasoning behind the systematic use of KF-based tracking approaches instead of the well-established PLL-based architectures from both theoretical and practical points of view. To support the discussion, two specific scenarios of interest to the aerospace community are numerically evaluated: robust carrier tracking of Global Navigation Satellite Systems' signals and synchronization in a deep space communications system.

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Section: A Conventional Pll Vs Standard Kfmentioning

confidence: 99%

mentioning

confidence: 99%

Are PLLs dead? A tutorial on kalman filter-based techniques for digital carrier synchronization

Vilà‐Valls

Closas

Navarro

et al. 2017

IEEE Aerosp. Electron. Syst. Mag.

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show abstract

“…The self‐healing prescaler presented in that aims to detect and heal malfunctions introduced by leakage current is too complicated in our opinion. Instead, we try to constrain the leakage current rather than fix it.…”

Section: True‐single‐phase‐clocking Prescaler With Stage‐merged Technmentioning

confidence: 99%

“…Process variability can lead to threshold voltage variations that degrade the device‐matching properties. Undesired leakage currents that deteriorate at ambient temperature degrade the accuracy of analog circuits and cause digital dynamic circuits to fail to work properly .…”

Section: Introductionmentioning

confidence: 99%

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A true single‐phase clock dual‐modulus prescaler with enhanced robustness against leakage currents

Jia

Wang

Yan

et al. 2016

Circuit Theory & Apps

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A new leakage-tolerant true single-phase clock dual-modulus prescaler based on a stage-merged scheme is presented. Leakage-restricting transistors are used to reduce the leakage currents at critical nodes, and leakage-related malfunctions are eliminated at minimal cost in terms of speed, power, and area overheads. An HSPICE simulation in a 40-nm process shows that the proposed divide-by-2/3 divider can effectively enhance robustness against leakage currents to extend the low frequency limit of the circuit over wide temperature and threshold voltage ranges. Additionally, the proposed design shows speed and power performance that is comparable with the performance levels of referenced designs.

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A 400 MHz–1.5 GHz all digital integer-N PLL with a reference spur reduction technique

Song¹,

Hwang²,

Kim³

et al. 2014

Analog Integr Circ Sig Process

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A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS

Cited by 9 publications

References 10 publications

Are PLLs dead? A tutorial on kalman filter-based techniques for digital carrier synchronization

Are PLLs dead? A tutorial on kalman filter-based techniques for digital carrier synchronization

A true single‐phase clock dual‐modulus prescaler with enhanced robustness against leakage currents

A 400 MHz–1.5 GHz all digital integer-N PLL with a reference spur reduction technique

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