A wideband CMOS sigma-delta modulator with incremental data weighted averaging

Kuo, Tai‐Haur; Chen, Kuan-Dar; Yeng, Horng-Ru

doi:10.1109/4.974541

Cited by 76 publications

(11 citation statements)

References 8 publications

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“…Fig.6 shows the output spectra for the proposed TI modulator with the modified NTF and the TI modulator with conventional NTF, without and with 0.1% channel mismatches. Here, the modified NTF is equation (6) and the conventional NTF is equation (5). Results show that the resolutions of both modulators are approximately equivalent without channel mismatches, but the SNDR degradation of the proposed TI modulator is only around 1.5dB and that of the TI modulator with conventional NTF is 9.3 dB, with 0.1% channel mismatches.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Recently, broadband and wideband applications require larger bandwidth for the ADCs, which create limitations when using sigma delta modulators (SDMs) [1][2][3]. In order to enlarge the bandwidth of the SDMs, the sampling clock frequency should increase even though high-order or multibit topologies are used [4,5]. However, the maximum sampling frequency of CMOS switched-capacitor (SC) circuit is limited by technology.…”

Section: Introductionmentioning

confidence: 99%

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A Novel Two-Channel Time-Interleaved Forth-Order Sigma-Delta Modulator Topology

Yang

Chen

Cheng

et al. 2008

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems

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Time-interleaved (TI) sigma-delta modulators are sensitive to channel-mismatches. In this paper, a new type of noise transfer function (NTF) which is a band-pass filter is adopted for the two-channel TI modulators to reduce the folded noise. Employing the concept of block digital filtering and theory of multirate operations, a novel two-channel TI highorder modulator is derived from the prototype of a conventional single-channel modulator. The simulation results show that the proposed modulator is insensitive to channel mismatches

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Novel Two-Channel Time-Interleaved Forth-Order Sigma-Delta Modulator Topology

Yang

Chen

Cheng

et al. 2008

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems

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“…A 5-bit capacitor DAC is used for the 1st integrator as shown in Fig. 2, the mismatches among the unit elements in a multibit DAC cause the harmonic distortion in the signal band, the data-weighted-averaging (DWA) logic circuit [11] is applied to the ΔΣAD modulator to reduce the influence of DAC nonlinearity errors. To illustrate the effect of the DWA logic circuit, the Monte Carlo analysis comparison with the proposed modulator is performed by MATLAB in 2 cases: (a) 4-bit DAC with ≤ 1% unit-capacitance random mismatches while DWA at ON mode; (b) 4-bit DAC with ≤ 1% unitcapacitance random mismatches while DWA at OFF mode.…”

Section: Multi-bit Dac and Dwa Logic Circuitmentioning

confidence: 99%

“…2 (a) is used for the 1st integrator. While the capacitor mismatches among the unit elements in a multi-bit DAC cause the harmonic distortion in the signal band, the DWA logic circuit [11] is applied to reduce the influence of DAC nonlinearity errors. Although the noise caused by the capacitor mismatch of DAC2 is injected into the ΔΣAD modulator from the input of the 2nd integrator, the non-linear noise is 1st-order shaped by the 1st integrator.…”

Section: Introductionmentioning

confidence: 99%

A Noise Coupled ΔΣAD Modulator Using Passive Adder Embedded Noise Shaping SAR Quantizer

Pan

San

2018

IEICE Trans. Electron.

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The usage of this PDF file must comply with the IEICE Provisions on Copyright. The author(s) can distribute this PDF file for research and educational (nonprofit) purposes only. Distribution by anyone other than the author(s) is prohibited. 480 SUMMARYThis paper presents a 3rd-order ΔΣAD modulator with noise coupling structure using the proposed passive adder embedded quantization noise shaping (QNS) SAR quantizer. QNS SAR quantizer can feedback shaped quantization noise and realize an additional 1st-order noise shaping by noise coupling technique. As a result, the 3rd-order noise coupled ΔΣAD modulator is realized by two integrators with ring amplifier and the QNS SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed ΔΣAD modulator in 90nm CMOS technology. Simulated SNDR of 81.05dB is achieved while a sinusoid −4.32dBFS input is sampled at 100MS/s and the bandwidth is BW = 3.125MHz. The total power consumption in the modulator is 4.58mW while the supply voltage is 1.2V.

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“…The imperfection of the analog components (primarily the finite op-amp gain) prevents the complete cancellation and under finite op-amp gain conditions a leakage of uncancelled 1 bit quantization noise occurs [10]. However this noise is the subject to a first order high pass filtering and thus reduced in the baseband.…”

Section: Proposed Dual Quantizer Low Distortion Sdmmentioning

confidence: 99%

Designs of multi-bit sigma delta modulator

Sonika

Neema

Patel

2016

Radioelectron.Commun.Syst.

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This paper presents new design variants of third order multi-bit sigma delta modulator (SDM): low distortion SDM and cascaded SDM. The proposed modulator based on the conventional SDM such L-0 MASH (Multi-stAge noise SHaping) and interstage feedback topology. The MASH SDM is not a single loop system. One of the drawback is that performance is limited by uncancelled noise from the first modulator and interstage feedback topology only cancels nonlinear errors introducing by multi-bit DAC in the final stage, but the rest stage still contains DAC nonlinearity errors without any noise shaping which still degrade overall system performance. An improved version of cascaded multi-bit SDM is proposed to overcome these problems mentioned above. In addition a third order low distortion SDM is also proposed. Simulation results verify the superiority of the both proposed modulator.

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A wideband CMOS sigma-delta modulator with incremental data weighted averaging

Cited by 76 publications

References 8 publications

A Novel Two-Channel Time-Interleaved Forth-Order Sigma-Delta Modulator Topology

A Novel Two-Channel Time-Interleaved Forth-Order Sigma-Delta Modulator Topology

A Noise Coupled ΔΣAD Modulator Using Passive Adder Embedded Noise Shaping SAR Quantizer

Designs of multi-bit sigma delta modulator

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