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An automatic-design methodology for designing high-tolerance modulator coefficients for high-order sigma-delta modulators (SDM's) from system specifications is presented. The methodology covers many design concerns including SDM coefficient tolerances for circuit component mismatch, stability, reduction of in-band tones, design tradeoffs among in-band noise suppression, oversampling ratio, and modulator order. Moreover, a high-order SDM synthesis tool (HOST) based on the methodology has been implemented in a C language program. Even for inexperienced designers, reliable and high-tolerance SDM coefficients for various applications can be automatically and efficiently generated using HOST. For synthesized SDM's with orders from three to eight and oversampling ratios from 32 to 256, coefficient variations within 2% (1% for the eighth order) are allowed and the resulting peak signal-to-noise ratio degradation is less than 3 dB. Several design examples synthesized by HOST are included.

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This paper presents a new offset current cancellation technique called multiple-path feedback compensation (MPFC) for greatly reducing offset currents at both output and internal nodes of SI circuits and systems. In order to analyze the effects and the statistical distribution of dc current offsets of large SI systems, a very simple and efficient SI model is first used. This model can be used for fast, accurate, statistical, and systematic analyzes of system characteristics such as offset current, frequency response, stability, scaling, and sensitivity. Based on the model, a complex SI system can be transferred to a simple signal flow graph, which can be represented by linear state equations. From the state equations, statistical Monte Carlo simulation is used to obtain optimal MPFC coefficients. A fifth-order Chebyshev SI filter is illustrated as an example for implementation and verification of the proposed MPFC technique. Ninety test chips have been fabricated with a 1-m CMOS n-well digital process.Increased percentages of circuit area and power consumption due to the use of the MPFC circuit are 5% and 4%, respectively. Measured results show that the variance of output offset currents is reduced to 2% of its original amount. Besides, the peak signalto-noise ratio (PSNR) is increased by 3 dB and the total harmonic distortion is reduced by 10 dB.

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