A Write Efficient PCM-Aware Sort

Vamsikrishna, Meduri Venkata; Su, Zhan; Tan, Kian-Lee

doi:10.1007/978-3-642-32600-4_8

Cited by 5 publications

(3 citation statements)

References 7 publications

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“…For example, [37] describes the necessary optimizations if sorting is to be applied over data in PCM. The authors propose and evaluate mechanisms for using a small DRAM buffer ahead of PCM to optimize performance.…”

Section: Query Processingmentioning

confidence: 46%

Data Management in Non-Volatile Memory

Viglas

2015

Proceedings of the 2015 ACM SIGMOD International Conference on Management of Data

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Non-volatile memory promises to bridge the gap between main memory and secondary storage by offering a universal storage device. Its performance profile is unique in that its latency is close to main memory and it is byte addressable, but it exhibits asymmetric I/O in that writes are more expensive than reads. These properties imply that it cannot act as a drop-in replacement for either main-memory or disk. Therefore, we must revisit the salient aspects of data management in light of this new technology. In what follows we present the current work in the area with a view towards identifying the open problems and exposing the research opportunities. In particular, we address issues like: (a) incorporating non-volatile memory into the data management stack, (b) supporting transactions and ensuring persistence and recovery, and (c) query processing.

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Section: Query Processingmentioning

confidence: 46%

Data Management in Non-Volatile Memory

Viglas

2015

Proceedings of the 2015 ACM SIGMOD International Conference on Management of Data

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“…With these underlying optimizations for drivers, FTL, and memory controller, the algorithms can directly benefit, but algorithms can also be optimized from a higher level. In this level, there are two ways to control or reduce NVM writes: One is to take advantage of extra caches [72,73] to mitigate NVM write requests with the help of DRAM; the other is to utilize the low-overhead NVM reads and in-time calculations to waive the costly NVM writes [58,74]. For further reducing NVM writes, even parts of constraints on data structures or algorithms [74][75][76] can be appropriately relaxed.…”

Section: Query Processing and Optimization In Platforms With New Hardmentioning

confidence: 99%

The New Hardware Development Trend and the Challenges in Data Management and Analysis

Pan

Zhang

et al. 2018

Data Sci. Eng.

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Hardware techniques and environments underwent significant transformations in the field of information technology, represented by high-performance processors and hardware accelerators characterized by abundant heterogeneous parallelism, nonvolatile memory with hybrid storage hierarchies, and RDMA-enabled high-speed network. Recent hardware trends in these areas deeply affect data management and analysis applications. In this paper, we first introduce the development trend of the new hardware in computation, storage, and network dimensions. Then, the related research techniques which affect the upper data management system design are reviewed. Finally, challenges and opportunities are addressed for the key technologies of data management and analysis in new hardware environments.

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“…Reducing movement is an important requirement among the many other reasons for choosing a given sorting algorithm, however different algorithms may result in different data movement patterns with different amounts of bit flips per move. While some have studied sorting on PCM [30], they focus on evaluating writes, not bit flips.…”

Section: Other Techniques Algorithms and Effectsmentioning

confidence: 99%

Designing Data Structures to Minimize Bit Flips on NVM

Bittman¹,

Gray²,

Raizes³

et al. 2018

2018 IEEE 7th Non-Volatile Memory Systems and Applications Symposium (NVMSA)

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The advent of byte-addressable non-volatile memory technologies such as phase change memory (PCM) has spurred a flurry of research on topics including consistency and durability of data structures across power failures and optimizing systems for the low-latency nature of these technologies, while typically aiming to increase lifetime and reduce power consumption by reducing the number of writes to the non-volatile memory. However, in technologies such as PCM, it is bit flips that consume power and wear out cells, not writes. Thus, PCM controllers do not rewrite cells unless the cell changes value. However, this crucial optimization, reducing the number of bits flipped, has not been sufficiently explored for the rest of the hardware and software stack. We develop a framework for using the number of bit flips as the measure of "goodness" for a range of hardware and software techniques. We also introduce several simple and straightforward modifications to existing data structures that can reduce the number of bit flips over time, and profile use cases in which the approach with the fewest writes does not also minimize bit flips. Based on these findings, we discuss potential approaches that can further minimize bit flips, better optimizing hardware and software for non-volatile memory technologies such as PCM.

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A Write Efficient PCM-Aware Sort

Cited by 5 publications

References 7 publications

Data Management in Non-Volatile Memory

Data Management in Non-Volatile Memory

The New Hardware Development Trend and the Challenges in Data Management and Analysis

Designing Data Structures to Minimize Bit Flips on NVM

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