A yield prediction model and cost of ownership for productivity enhancement beyond imec 5nm technology node

Tsai, Yi-Pei; Chang, Yi-Han; Wang, Jane; Trivkovic, Darko; Ronse, Kurt G.; Kim, Ryoung-Han

doi:10.1117/12.2617415

Cited by 5 publications

(5 citation statements)

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“…Critical masks are defined as the number of masks required to pattern the most advanced modules in a technology. [3] The result of this model is represented in Figure 2c for mobile and HPC, considering for each the average area extracted from [1]. For mobile applications the relative yield reduction in advanced nodes is less pronounced than in HPC.…”

Section: Wafer Cost and Yield Modelmentioning

confidence: 99%

Investigation of die-cost scaling scenarios in future technologies

Mirabelli,

Tsai,

Chang

et al. 2024

DTCO and Computational Patterning III

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The concurrent saturation in dimensional scaling and increase in manufacturing cost and complexity has caused the overall semiconductor manufacturing cost to significantly increase. As a result, the cost per transistor is predicted to sharply increase in future technologies, deviating from the typical 30% cost per transistor reduction. This work explores the use of 3D-integration technologies, as wafer-to-wafer hybrid bonding, for both mobile and high-performance application. It is observed that the use of 3D-integration schemes, can reduce the overall die cost at same functionality, paving the way for cost-effective scaling solutions in future technologies.

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Section: Wafer Cost and Yield Modelmentioning

confidence: 99%

Investigation of die-cost scaling scenarios in future technologies

Mirabelli,

Tsai,

Chang

et al. 2024

DTCO and Computational Patterning III

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“…The module block diagram of the cost of ownership (CoO) published in our previous study [6] shows that the process flow for a certain node includes multiple layers, each representing its process block and module. Each module can expand to multiple classes and sub-classes, and each class and sub-class can be evaluated as a cost.…”

Section: Cost Assumption For Euv and High Na Euvmentioning

confidence: 99%

“…In our previous study, we have introduced the wafer yield and wafer cost on FinFET structures and patterning techiques which utilize EUV lithography [6]. In this study, we focus on the yield and cost of more inovating device structures such as Nanosheet (NSh), Forksheet (FSh), and CFET.…”

Section: Introductionmentioning

confidence: 99%

Productivity enhancement study: yield, cost, and turn-around-time modeling for EUV and high NA EUV

Tsai

Chang

Wang

et al. 2023

DTCO and Computational Patterning II

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A yield prediction model with a corresponding cost of the ownership (CoO) and turn-around-time (TAT) analysis is studied on imec’s advanced technology nodes that include EUV and high NA EUV lithography. It also captures device variations from FinFET to CFET. Using modeled die-yield and the cost-of-ownership (CoO) for imec advanced technology nodes including N2, A14, A10, A7 to A5 technology nodes, we show there is a clear correlation trend in choosing a process technology. A precise methodology that can co-model the turn-around-time (TAT) which is inseparable in evaluating the manufacturability is also provided. As a conclusion, node-to-node scalability is proven to be a function of the manufacturability which will be represented to the yield, CoO and TAT metric, not just a function of the patterning complexity or photolithographic resolution that the industry is mainly chasing after.

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“…[1][2][3][4][5][6] The next generation of EUVL, using a high numerical aperture (NA) of 0.55 compared to the present 0.33, is in development and scheduled for production within the next few years. [7][8][9][10][11][12][13][14][15][16][17][18][19] However, the shift to a higher NA will lead to reduced depth of focus (DOF), as shown in the following equation: 20)…”

Section: Introductionmentioning

confidence: 99%

Pattern deformation mitigation for EUV photoresists using wafer backside cleaning techniques

Harumoto,

Figueiredo dos Santos,

Zanders

et al. 2024

Jpn. J. Appl. Phys.

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This study delves into the effects of wafer backside particles on pattern defocus in extreme ultraviolet lithography (EUVL). Additionally, the potential mitigation of this pattern defocus was examined through wafer backside cleaning. Comparative analyses were conducted between EUVL patterning tests performed using wafers with contaminated and cleaned wafer backside. Defocus points and abnormal critical dimensions (CDs) on the photoresist patterns at the wafer frontside were detected using scanning electron microscopy and optical CD measurement, respectively. The specific locations of these defocus or abnormal CD points were compared and confirmed to be correlated with particles that were present on the same locations on the backside of the wafer. Furthermore, it was found that an effective backside cleaning process can mitigate pattern defocus caused by these wafer backside particles.

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A yield prediction model and cost of ownership for productivity enhancement beyond imec 5nm technology node

Cited by 5 publications

References 0 publications

Investigation of die-cost scaling scenarios in future technologies

Investigation of die-cost scaling scenarios in future technologies

Productivity enhancement study: yield, cost, and turn-around-time modeling for EUV and high NA EUV

Pattern deformation mitigation for EUV photoresists using wafer backside cleaning techniques

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