Abnormal Failure Behavior of Sn-3.5Ag Solder Bumps Under Excessive Electric Current Stressing Conditions

Abstract

Abnormal failure behavior of flip chip Sn-3.5Ag solder bumps with a Cu underbump metallurgy under excessive electric current stressing conditions is investigated with regard to electromigration lifetime characteristics and damage evolution morphologies. Abnormal behavior such as abrupt changes in the slope of the resistance versus stressing time curve correlate well with the changes in mean time to failure and the standard deviation with respect to the resistance increase ratio, which seems to be strongly related to highly accelerated electromigration test conditions of 120°C to 160°C and 3 9 10 4 A/cm 2 to 4.6 9 10 4 A/cm 2 . This is closely related to changes in the damage evolution mechanism with time, even though the activation energy for electrical failure is primarily controlled by Cu diffusion through Cu-Sn intermetallic compound layers.

Interfacial Reaction Effect on Electrical Reliability of Cu Pillar/Sn Bumps

“…19 When the specimen undergoes constant current stressing over time, the joints of the FCSBs become a reliability issue due to EM. 9 This damage by EM increases the electrical resistance of the overall Cu pillar/Sn bump system. Therefore, comparing the measured resistance with the microstructure of the specimen can provide information on the electrical failure mechanism.…”

“…Even though sample-tosample variations are apparent, there seems to be a common resistance-time relationship. 9 Cu pillar/Sn bumps were current-stressed for longer than 560 h before a 20% increase in resistance was reached. Measured resistance changes were correlated with the interfacial microstructure evolution observed during current stressing.…”

“…28,29 The excellent EM characteristics of Cu pillar/Sn bumps can be compared with the characteristics of solder joints with a diameter similar to the pad. According to the reports by Lee et al 2,9,10 where Sn-Ag solder joints with diameters of 100 lm were formed on the Cu under bump metallization (UBM), the mean time to failure of those devices was about 30 h to 150 h. In contrast, 600 h passed before EM failure occurred in the Cu pillar/Sn bump structure. Therefore, compared with conventional solder bumps, the Cu pillar/Sn bump structure has excellent electrical reliability.…”

“…Similar experimental methods are reported in detail elsewhere. [9][10][11][12] The evolution of each interfacial microstructure and the IMC growth in the Cu pillar/Sn bumps was analyzed using SEM in backscattered electron (BSE) mode and using energy-dispersive x-ray spectroscopy (EDS). IMC thickness was measured from the IMC layers at both the chip and substrate sides.…”

Investigating the Formation Process of Sn‐Based Lead‐Free Nanoparticles with a Chemical Reduction Method

“…However, the very nature of the levels of toxicity with lead in this system has been a persistent issue and is, therefore, being phased out in the electronic industry gradually. The development of viable alternatives has focused on many alloy-based systems, such as Sn-Cu [1], Sn-Ag [2], Sn-Zn [3], Sn-Bi [4], and Sn-In [5]. To improve the properties of these binary alloy solders, a third element can be introduced.…”