Interfacial Reaction Effect on Electrical Reliability of Cu Pillar/Sn Bumps

Jeong, Myung-Yung; Lim, Gi-Tae; Kim, Byoung-Joon; Lee, Kiwook; Kim, Jae-Dong; Joo, Young‐Chang; Park, Young-Bae

doi:10.1007/s11664-010-1345-7

Cited by 22 publications

(5 citation statements)

References 23 publications

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“…Previous studies pointed out that some level of porosity at the Cu/”SN” solder interface cannot be avoided due to the coalescence of atomic-level vacancies into the so-called Kirkendall voids [ 44 , 45 , 46 , 47 ]. According to [ 47 ], the Kirkendall voids could be formed due to electromigration effects, where high current densities (in order of 10 8 A/m 2 ) are present.…”

Section: Resultsmentioning

confidence: 99%

Thermal Cycling of (RE)BCO-Based Superconducting Tapes Joined by Lead-Free Solders

et al. 2021

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We prepared overlap soldered joints of high-temperature superconducting tapes, using various materials and preparation conditions. In order to select the joints with optimal performance, we correlated their electrical properties (derived from current–voltage curves) with the microstructure of the respective joint cross-section by scanning electron microscopy. With the first group of joints, we focused on the effect of used materials on joint resistivity and critical current, and we found that the dominant role was played by the quality of the internal interfaces of the superconducting tape. Initial joint resistivities ranged in the first group from 41 to 341 nΩ·cm2. The second group of joints underwent a series of thermal cyclings, upon which the initial resistivity range of 35‒49 nΩ·cm2 broadened to 25‒128 nΩ·cm2. After the total of 135 thermal cycles, three out of four joints showed no signs of significant degradation. Within the limit of 100 thermal cycles, reliable soldered joints can be thus prepared, with normalized resistivity not exceeding 1.4 and with normalized critical current above the value of 0.85.

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Section: Resultsmentioning

confidence: 99%

Thermal Cycling of (RE)BCO-Based Superconducting Tapes Joined by Lead-Free Solders

et al. 2021

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“…The gap height for molded underfill between the RF-filter and the module substrate can easily be adjusted by the CPB Cu base height. Better electrical reliability of CPBs compared to SBs was supposed in [7]. The potential of saving chip area by using CPBs instead of SBs on TFAP following present design rules is illustrated in Fig.…”

Section: Introductionmentioning

confidence: 90%

Reliability Study of Miniaturized Surface Acoustic Wave RF-Filters With Copper Pillar Bump Interconnections

Schober

Eulenkamp

Nicolaus³

et al. 2021

IEEE Access

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Microacoustic radio frequency filters are essential electronic components for all devices using wireless communication. For miniaturization and cost reduction it is necessary to further reduce the area for the electrical contacts on the chip. CPB (copper pillar bump) interconnections on radio frequency filters can release valuable chip design area of up to 26 % compared to standard SB (solder bump) interconnections on a Qualcomm TFAP (Thin Film Acoustic Package). We developed a process to deposit CPB interconnections on microacoustic radio frequency filters. A 1.20 mm  1.60 mm SAW (surface acoustic wave) LTE (Long Term Evolution) band 26 duplexer with a height of 0.20 mm including the CPB interconnections was investigated. Unbiased highly accelerated stress test, damp heat steady state, dry heat, and temperature cycling reliability tests have shown that the new interconnection technology fulfills the reliability requirements of the smart device industry. Two failure modes caused by extended temperature cycling reliability were identified via scanning acoustic microscopy and scanning electron microscopy analyses on cross sections.

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“…Four bonded die pairs were utilized to test the bump resistance and evaluate the conductivity of the daisy-chain structure using a manual probing station (PE-4, Ever Being, Inc.). The daisy-chain channel comprises 64 bonded bumps, Al RDL layers, and test pads, whose theoretical resistance values are shown in table 4 [34,35].…”

Section: Electrical Measurementmentioning

confidence: 99%

Low-temperature, short-time, wafer-level bonding for Cu/Sn/Cu solid-state-diffusion interconnect in 3-D integration

Li¹,

Wang²,

Li³

et al. 2023

Phys. Scr.

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In this paper, Cu/Sn/Cu solid-state diffusion (SSD) under low temperature is proposed and investigated for three-dimensional (3-D) integration. Cu and Sn films were deposited by high-efficiency and low-cost physical vapor deposition to fabricate 40-µm-pitch daisy-chain structures. Subsequently, the Cu bump surface was treated with Ar (5% H2) plasma. The Cu/Sn/Cu structure was bonded face to face at 200 ℃ for 15 min. The interfacial composition of the as-bonded dies comprised five layers, Cu/Cu3Sn/Cu6Sn5/Cu3Sn/Cu, with no Sn remaining and no overflow. After annealing at 200 ℃ for 15 min under N2 atmosphere, as the Cu6Sn5 completely transformed into Cu3Sn, the microstructure changed to stable three layers: Cu/Cu3Sn/Cu. Additionally, the average bonding shear strength reached 27.0 MPa, which is higher than that for conventional Cu/Sn SSD bonding. The measured bonding resistance value was maintained at the theoretical value. Moreover, the parabolic growth constant of Cu3Sn reached 1.86×10−15 m2/s. Our study demonstrates the feasibility of using Cu/Sn/Cu SSD for low-temperature, short-time, wafer-level bonding.

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Interfacial Reaction Effect on Electrical Reliability of Cu Pillar/Sn Bumps

Cited by 22 publications

References 23 publications

Thermal Cycling of (RE)BCO-Based Superconducting Tapes Joined by Lead-Free Solders

Thermal Cycling of (RE)BCO-Based Superconducting Tapes Joined by Lead-Free Solders

Reliability Study of Miniaturized Surface Acoustic Wave RF-Filters With Copper Pillar Bump Interconnections

Low-temperature, short-time, wafer-level bonding for Cu/Sn/Cu solid-state-diffusion interconnect in 3-D integration

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