About carries and tokens: re-using adder circuits for arbitration

Preuber, T.B.; Zabel, Martin; Spallek, Rainer G.

doi:10.1109/sips.2005.1579839

Cited by 6 publications

(2 citation statements)

References 9 publications

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“…Preußer et al described the analogies among the carry propagation of addition and token-based arbitration to derive an optimized mapping of arbiter circuits by a manual low-level implementation [4]. This group later presents a generalized approach, which enables the highlevel and portable description of carry-chain computations by the standard addition operator [5].…”

Section: A Generalized Carry-chain Usagementioning

confidence: 99%

Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains

Preußer

Spallek

2010

2010 International Conference on Field Programmable Logic and Applications

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This paper presents an approach to the automatic mapping of arbitrary combinational circuits to the arithmetic carry-chain structures widely available in modern FPGAs. This capability is highly valuable as it enables the utilization of these fast special-purpose structures for general-purpose logic. The described approach is both automatic and generally applicable to all carry-chain architectures designed for binary addition. It, thus, lifts severe constraints left by previous works. It helps to reduce the pressure on the general-purpose routing resources and accelerates critical logic paths. The proposed mapping is further shown to enhance the logic capability of a logic block containing a k-input lookup table (k-LUT) to implement many (k + 1)-input functions on common FPGA architectures. This, in particular, also applies to all logic functions with a noninverting path as introduced by Anderson and Wang [1]. This makes their envisioned gains in logic density achievable even on current devices without requiring their architectural extension. The benefits of the carry-chain mapping are experimentally evaluated on the basis of combinational MCNC benchmarks. It is shown how carry chains can be recovered within a functional standard mapping and that a device mapping aware of carry chains achieves a reduction of the combinational delay of about a 20 percent.

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Section: A Generalized Carry-chain Usagementioning

confidence: 99%

Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains

Preußer

Spallek

2010

2010 International Conference on Field Programmable Logic and Applications

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“…This particular use case (without intermediate prefix results) is even enjoying some but no consistent support by a few of the latest synthesis tools. Another use was demonstrated for token-based arbitration schemes [7], which, however, require a device-specific, low-level design to achieve such a mapping. An automated mapping of deep logic chains to carry chains was described by Frederick and Somani [8].…”

Section: Related Workmentioning

confidence: 99%

Mapping basic prefix computations to fast carry-chain structures

Preußer

Spallek

2009

2009 International Conference on Field Programmable Logic and Applications

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Carry chains are a standard feature of modern FPGA architectures. They enable compact, regular and yet very fast implementations of the binary word addition even outpacing sophisticated parallel prefix networks for bit width far beyond 100. Although they are equally suited for other simple prefix computations, their employment in the implementation of such user functions is hindered by unportable lowlevel and vendor-or even device-specific means to implement the desired mapping. This paper names suitable example applications, identifies the class of prefix computations generically mappable to carry chains and presents a universal procedure to achieve this mapping by a transformation building upon the well-supported binary word addition. Synthesis results are presented to illustrate both the gain in speed and the significant reduction of area through the employment of this approach.

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