Mapping basic prefix computations to fast carry-chain structures

Abstract

Carry chains are a standard feature of modern FPGA architectures. They enable compact, regular and yet very fast implementations of the binary word addition even outpacing sophisticated parallel prefix networks for bit width far beyond 100. Although they are equally suited for other simple prefix computations, their employment in the implementation of such user functions is hindered by unportable lowlevel and vendor-or even device-specific means to implement the desired mapping. This paper names suitable example applications, identifies the class of prefix computations generically mappable to carry chains and presents a universal procedure to achieve this mapping by a transformation building upon the well-supported binary word addition. Synthesis results are presented to illustrate both the gain in speed and the significant reduction of area through the employment of this approach.

FPGA-Specific Arithmetic Optimizations of Short-Latency Adders

“…The current study presents a novel mapping of the multiplexer network to the carry chain based on the work of Preußer et al [9] on mapping general prefix computations to the carrychain. The multiplexer network is mapped to one k-bit RCA and a carry-recovery circuit which, most of the time may be fused with other computations in modern FPGA.…”

“…To compete with the fast carry propagation within a block, the inter-block carry propagation must also exploit the available carry-chain structures. This will be achieved by the technique described by Preußer and Spallek [9].…”

Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains

“…Preußer et al described the analogies among the carry propagation of addition and token-based arbitration to derive an optimized mapping of arbiter circuits by a manual low-level implementation [4]. This group later presents a generalized approach, which enables the highlevel and portable description of carry-chain computations by the standard addition operator [5]. Although this approach is, in principle, applicable to the mapping of arbitrary logic, such practice is infeasible due to the required manual identification of the mappable logic paths.…”

A Fabric Component Based Approach to the Architecture and Design Automation of High-Performance Integer Arithmetic Circuits on FPGA

“…Often, the logic synthesis tools are unable to infer the desired native circuit components from the input HDL, as they explore only a small design space close to the input architectural description [11]. The logic synthesis algorithms are also unable to apply the logic identities and perform appropriate algebraic factoring and sub-expression sharing in many cases, especially when intermediate signals are tapped out [2] or registered to facilitate pipelining of the architecture. It is in general a nontrivial computational problem to decompose the Boolean equations describing the implemented circuit, to forms such that the sub-expressions can be mapped easily and efficiently to the fabric primitives on the target FPGA.…”

“…It can also infer wide function multiplexers native to an FPGA slice, thereby achieving speedup by avoiding switch-box routing to the extent possible. However, it fails to do all of this, as soon as the final carry outputs of individual slices [2] or Lookup Table (LUT) outputs are tapped out or registered to facilitate pipelining of the architecture. In such a scenario, the designer has to spell out special directives in the HDL of the design or in the associated "constraints files," so that in the packing or clustering step (as known in the FPGA CAD literature [3]) of the FPGA design flow, the desired technology mapped circuit is efficiently "packed" into the available hardware resources.…”