Abstraction techniques to improve scalability of equivalence verification for NCL circuits

Wijayasekara, Vidura; Rollie, A.T.; Hodges, Reed; Srinivasan, Sudarshan K.; Smith, Scott C.

doi:10.1049/el.2016.1138

Cited by 3 publications

(2 citation statements)

References 8 publications

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“…As a result, the synthesized NCL structures differ significantly from their synchronous specifications. A few formal verification methods have also been developed to verify the safety (functional correctness) and liveness (deadlock-free operation) of the synthesized NCL circuits [13][14][15]. However, these formal methods are only applicable to conventional NCL architectures.…”

Section: Introductionmentioning

confidence: 99%

A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits

Mazumder,

Datta,

Bodoh

et al. 2024

JLPEA

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The increasing demand for high-speed, energy-efficient, and miniaturized electronics has led to significant challenges and compromises in the domain of conventional clock-based digital designs, most notably reduced circuit reliability, particularly in mission-critical hardware. At scaled technology nodes, devices are vulnerable to transient or soft errors, such as Single Event Upset (SEU) and Single Event Latch-up (SEL). External radiation, internal electromagnetic interference (EMI), or noise are the primary sources of these errors, which can compromise the circuit functionality. In response to these challenges, the Quasi-Delay-Insensitive (QDI) Null Convention Logic (NCL) asynchronous design paradigm has emerged as a promising alternative, offering advantages such as ultra-low power performance, reduced noise and EMI, and resilience to process, voltage, and temperature variations. Moreover, its unique architecture and insensitivity to timing variations offers a degree of resistance against transient errors; however, it is not entirely resilient. Several resiliency schemes are available to detect and mitigate soft errors in QDI circuits, with approaches based on redundancy proving to be the most effective in ensuring complete resilience across all major QDI implementation paradigms, including NCL, Pre-charge/Weak-charge Half Buffers (PCHB/WCHB), and Sleep Convention Logic (SCL). This research focuses on one such redundancy-based resiliency scheme for QDI NCL circuits, known as the dual-modular redundancy-based NCL (DMR-NCL) architecture, and addresses the absence of formal methods for the verification and analysis of such circuits. A novel methodology has been proposed for formally verifying the correctness of DMR-NCL circuits synthesized from their synchronous counterparts, covering both safety (functional correctness) and liveness (the absence of deadlock). In addition, this research introduces a formal framework for the vulnerability analysis of DMR-NCL circuits against SEU/SEL. To demonstrate the framework’s efficacy and scalability, a prototype computer-aided support tool has been developed, which verifies and analyzes multiple DMR-NCL benchmark circuits of varying sizes and complexities.

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Section: Introductionmentioning

confidence: 99%

A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits

Mazumder,

Datta,

Bodoh

et al. 2024

JLPEA

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“…There have also been several formal verification approaches to check safety and liveness of NCL circuits [8,9]; however, safety and liveness verification does not guarantee input completeness, which has to be verified independently.…”

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confidence: 99%

Automated verification of input completeness for NCL circuits

Srinivasan

Smith

2018

Electron. lett.

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An automated formal verification approach for ensuring input completeness of NULL Convention Logic (NCL) circuits is proposed. NCL circuits have the benefit that they can operate in extreme environments where traditional synchronous circuits fail due to significant fluctuations in circuit timing. Input completeness is a critical property to ensure correct functioning of NCL circuits in extreme environments and therefore is required to be verified. Note that an NCL circuit can be functionally correct and still not be input complete, which could cause the circuit to operate correctly under normal conditions, but malfunction only when the circuit timing is substantially changed (e.g. operating in a very hot or cold environment such as outer space).

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An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits

Hossain

Sakib

Srinivasan

et al. 2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstraction techniques to improve scalability of equivalence verification for NCL circuits

Cited by 3 publications

References 8 publications

A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits

A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits

Automated verification of input completeness for NCL circuits

An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits

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