AC-Capacitance Techniques for Interface Trap Analysis in GaN-Based Buried-Channel MIS-HEMTs

Yang, Shu; Liu, Shenghou; Lu, Yunyou; Liu, Cheng; Chen, Kevin J.

doi:10.1109/ted.2015.2420690

Cited by 86 publications

(29 citation statements)

References 25 publications

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“…Fig. 7 shows the interface trap density distributions at the dielectrics/GaN interface for the MIS-capacitor structures obtained from the interface state density -energy level mapping method [19]. The means value and the standard deviation of interface trap density were plotted in the inserted figure that was extracted from 8 representative devices for each sample.…”

Section: Resultsmentioning

confidence: 99%

Effect of High-k Passivation Layer on High Voltage Properties of GaN Metal-Insulator-Semiconductor Devices

et al. 2020

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In this paper, the GaN-based MIS-HEMTs with Si 3 N 4 single-layer passivation, Al 2 O 3 /SiN x bilayer passivation, and ZrO 2 /SiN x bilayer passivation are demonstrated. High-k dielectrics are adopted as the passivation layer on MIS-HEMTs to suppress the shallow traps on the GaN surface. Besides, high permittivity dielectrics passivated MIS-HEMTs also show an improved breakdown voltage characteristic, and that is explained by 2-D simulation analysis. The fabricated devices with high-k dielectrics/SiN x bilayer passivation exhibit higher power properties than the devices with plasma enhanced chemical vapor deposition-SiN x single layer passivation, including smaller current collapse and higher breakdown voltage. The Al 2 O 3 /SiN x passivated MIS-HEMTs exhibit a breakdown voltage of 1092 V, and the dynamic R on is only 1.14 times the static R on after off-state V DS stress of 150 V. On the other hand, the ZrO 2 /SiN x passivated MIS-HEMTs exhibit a higher breakdown voltage of 1207 V, and the dynamic R on is 1.25 times the static R on after off-state V DS stress of 150 V. INDEX TERMS AlGaN/GaN, MIS-HEMTs, Si 3 N 4 , high-k, Al 2 O 3 , ZrO 2 , current collapse, dynamic on-resistance, breakdown voltage.

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Section: Resultsmentioning

confidence: 99%

Effect of High-k Passivation Layer on High Voltage Properties of GaN Metal-Insulator-Semiconductor Devices

et al. 2020

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“…This phenomenon occurs because larger number of deep traps with long emission time constants appear in the SiON and SiO 2 MIS structure. We also used dielectric capacitance in series with the barrier capacitance model to extract the Cox of the three samples [36]. The Cox is 297.86, 277.82, and 364.82 nF/cm −2 for SiN x , SiON, and SiO 2 MIS-HEMT, respectively.…”

Section: Resultsmentioning

confidence: 99%

AlGaN/GaN MIS-HEMT with PECVD SiNx, SiON, SiO2 as Gate Dielectric and Passivation Layer

et al. 2018

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Three different insulator layers SiNx, SiON, and SiO2 were used as a gate dielectric and passivation layer in AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMT). The SiNx, SiON, and SiO2 were deposited by a plasma-enhanced chemical vapor deposition (PECVD) system. Great differences in the gate leakage current, breakdown voltage, interface traps, and current collapse were observed. The SiON MIS-HEMT exhibited the highest breakdown voltage and Ion/Ioff ratio. The SiNx MIS-HEMT performed well in current collapse but exhibited the highest gate leakage current density. The SiO2 MIS-HEMT possessed the lowest gate leakage current density but suffered from the early breakdown of the metal–insulator–semiconductor (MIS) diode. As for interface traps, the SiNx MIS-HEMT has the largest shallow trap density and the lowest deep trap density. The SiO2 MIS-HEMT has the largest deep trap density. The factors causing current collapse were confirmed by Photoluminescence (PL) spectra. Based on the direct current (DC) characteristics, SiNx and SiON both have advantages and disadvantages.

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“…A larger ΔV FB indicates more interface trapped charges. The corresponding interface trapped charge density is quantified using the following equation [43]:…”

Section: Resultsmentioning

confidence: 99%

Interface passivation and trap reduction via hydrogen fluoride for molybdenum disulfide on silicon oxide back-gate transistors

Hu¹,

Yip²,

Tang³

et al. 2018

Semicond. Sci. Technol.

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Layered semiconductor molybdenum disulfide (MoS 2) has recently emerged as a promising material for flexible electronic and optoelectronic devices because of its finite bandgap and high degree of gate control. Here, we report a hydrogen fluoride (HF) passivation technique for improving the carrier mobility and interface quality of chemical vapor deposited monolayer MoS 2 on a SiO 2 /Si substrate. After passivation, the fabricated MoS 2 back-gate transistors demonstrate a more than double improvement in average electron mobility, a reduced gate hysteresis gap of 3 V, and a low interface trapped charge density of ∼5.8×10 11 cm −2. The improvements are attributed to the satisfied interface dangling bonds, thus a reduction of interface trap states and trapped charges. Surface x-ray photoelectron spectroscopy analysis and first-principles simulation were performed to verify the HF passivation effect. The results here highlight the necessity of a MoS 2 /dielectric passivation strategy and provides a viable route for enhancing the performance of MoS 2 nano-electronic devices.

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AC-Capacitance Techniques for Interface Trap Analysis in GaN-Based Buried-Channel MIS-HEMTs

Cited by 86 publications

References 25 publications

Effect of High-k Passivation Layer on High Voltage Properties of GaN Metal-Insulator-Semiconductor Devices

Effect of High-k Passivation Layer on High Voltage Properties of GaN Metal-Insulator-Semiconductor Devices

AlGaN/GaN MIS-HEMT with PECVD SiNx, SiON, SiO2 as Gate Dielectric and Passivation Layer

Interface passivation and trap reduction via hydrogen fluoride for molybdenum disulfide on silicon oxide back-gate transistors

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