Acceldroid: Co-designed acceleration of Android bytecode

Abstract

A hardware/software co-designed processor transparently supports a ubiquitous ISA (e.g. x86) with diversified and innovative microarchitectural implementations.It leverages co-designed HW features and dynamic binary translation (DBT) SW to morph existing binary programs to scale performance and save power. On such systems, the portable bytecode of modern dynamic languages (e.g. Java, JavaScript, etc.) is first translated into the code in the architecture ISA by the just-in-time (JIT) compilation in the bytecode virtual machine, and then into the code in the internal implementation ISA by the DBT. This not only incurs the translation overheads twice, but also brings significant emulation inefficiency as the DBT does not have the high level bytecode information. In this paper, we present AccelDroid, which accelerates the Android Dalvik bytecode execution on the HW/SW co-designed processor through direct bytecode translation in the DBT. Our experiments on a HW/SW co-designed Transmeta Efficeon machine show that AccelDroid can improve performance by 78% and save energy by 40% for the CaffeineMark 3.0 benchmark suite. OverheadsCustomized HW/SW Co-Design

A Survey of Performance Optimization for Mobile Applications

“…For a high responsiveness of mobile applications, developers apply several categories of optimization approaches. In the [68] 2011 EuroSys Ra et al [69] 2011 MobiSys Kosta et al [70] 2012 INFOCOM Gordon et al [71] 2012 OSDI Gordon et al [72] 2015 MobiSys Das et al [46] 2016 IACC Montella et al [73] 2017 CCPE Chen and Hao [74] 2018 J-Sac Antipatterns Jin et al [75] 2012 SIGPLAN Yang et al [53] 2013 MOBS Nistor et al [76] 2013 ICSE Liu et al [13] 2014 ICSE Ongkosit and Takada [77] 2014 DeMobile Hecht et al [78] 2015 ASE Habchi et al [79] 2018 ASE Hecht et al [51] 2016 MobileSoft Li et al [80] 2019 SANER Refactoring Lin et al [81] 2014 FSE Okur et al [82] 2014 ICSE Lin et al [83] 2015 ASE Lyu et al [47] 2018 ISSTA Feng et al [84] 2019 ICSTW Prefetching Higgins et al [85] 2012 MobiSys Zhao et al [86] 2018 ICSE Choi et al [87] 2018 CoNEXT Malavolta et al [88] 2019 ICSE-NIER Programming languages Batyuk et al [89] 2009 MobileWare Lee and Jeon [90] 2010 ICCAS Lee and Lee [91] 2011 iCast Lin et al [92] 2011 IBICA Saborido et al [45] 2018 EMSE CPU & GPU Wang et al [93] 2013 CGO Cheng et al [94] 2013 IWSSIP Thongkaew et al [95] 2015 JIP I/O operations Nguyen et al [50] 2015 MobiSys Mao et al [96] 2018 ITCSDI…”

“…Android provides the Native Development Kit (NDK) that allows developers to write native C/C++ code. Native instructions are directly executed by the CPU and, therefore, they provide a better performance over non-native ones [93], [99]. Several empirical studies compared the performance of programming languages, and found that native C code reduces the running time of the same algorithms written in Dalvik Java code [92], [90], [91], [89].…”

Static Dalvik Bytecode Optimization for Android Applications

“…Modifying DVM causes maintenance problems since DVM is under active development. AccelDroid [13] is the HW/SW co-designed system for accelerating Android applications. To boost the power and performance efficiency of Android applications, a Dalvik bytecode-aware processor is implemented by codesigning hardware and software; this is so that Dalvik bytecodes can be executed directly using dynamic binary translation on the special processor.…”

“…Previous studies to improve the performance of Android applications can be largely classified into two areas -those that adopt complementary compilations of DVM [10]- [11] and those that adopt modifications of DVM [4], [11]- [13]. However, previous studies have yet to adequately apply their optimization techniques to new versions of DVM because their techniques adopt the unique compilation on a particular version of DVM and a special hardware support.…”

Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment

“…HW/SW codesigned processors [Dehnert et al 2003;Ebcioglu et al 1997;Sathaye et al 1999] have enticed researchers for more than a decade. Moreover, there is a renewed interest in them in both the industry and academia [Lupon et al 2014;Branković et al 2014;Wang et al 2013;Pavlou et al 2012;Neelakantam et al 2010]. These processors employ a software layer that resides between the hardware and the operating system.…”