Accelerating FinFET MOL Process Development Using Design for Inspection Methodology

Wu, Fangrui; Yang, Linrong; Li, Runling; Ye, Chiung-Han; Zhang, Haiqiong; Hsu, Ikai; Brozek, Tomasz; Yu, Bo

doi:10.1109/asmc54647.2022.9792513

Cited by 1 publication

(1 citation statement)

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“…The test structure design is routed as a chain structure, comprised of the metal collector pad, the Design-of-Interest (DOI) and the design construct providing a grounding path (GND). The DOI part represents the area dedicated to the target failure mode, in this case metal-via open (more use case examples can be found in [6]. To perform the test of such structure with e-Beam, only the VC signal from the metal collector pad needs to be collected, as shown in Fig.…”

Section: Design-for-inspection Tm (Dfi) Metrologymentioning

confidence: 99%

Application of e-Beam Voltage Contrast Technique for Overlay Improvement and Process Window Control in Multi-Patterning Interconnect Scheme

Yang

Hsu

et al. 2022

IEEE J. Electron Devices Soc.

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Interconnect development for the new technology node requires coordinated efforts of multiple module teams working to co-optimize patterning and metallization solutions to meet performance and yield, and reliability targets. This paper presents the results of interconnect patterning optimization to improve overlay and process window control using a novel methodology, Design-for-Inspection™ (DFI). Using design-assisted voltage contrast measurement techniques, the method enables in-line test and monitoring of process induced overlay and CD variation of back-end-of line (BEOL) features built with litho-etch-litho-etch (LELE) patterning. While only some of the features of multi-color patterning scheme are chosen to be aligned directly, other combination of metal line and via colors may have uncontrolled misalignment risking open or short failures. The paper shows how the complete metrology coverage of multi-color combinations between dual patterned via and dual patterned metal lines helps driving the improvement of overlay and process margins in 14nm technology. The optimized process margin for via opens enables higher yields and better reliability.

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Section: Design-for-inspection Tm (Dfi) Metrologymentioning

confidence: 99%