2010 International Conference on Field-Programmable Technology 2010
DOI: 10.1109/fpt.2010.5681755
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Accelerating HMMER on FPGA using parallel prefixes and reductions

Abstract: HMMER est un outil basé sur la notion prols à base modèles de Markov cachés, qui est très largement utilisé en bio-informatique. Les parties critiques de lâalgorithme (fonctions MSV et P7Viterbi) utilisées dans HMMER sont très consommatrices en temps de calcul et réputées très diciles à paralléliser. Dans cet article, nous proposons un schéma de parallélisation original pour HMMER, basé sur une reformulation mathématique de lâalgorithme qui permet de découvrir de nouvelles possibilités de parallélisation bien … Show more

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Cited by 10 publications
(6 citation statements)
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“…The original work [ 2 ] yields 12 GCUPS on MSVFilter and 1.6 GCUPS on ViterbiFilter by single core of an Intel processor. Acceleration via high-end FPGA designs in [ 15 ] yields upto 81 GCUPS for MSV and 3.6 GCUPS for P7Viterbi; GPUHMMER [ 6 ], an outdated acceleration with roughly 1.48 GCUPS, was modified by Lin [ 17 ] to accelerate MSVFilter in HMMER 3.x, which yields upto 32.8 GCUPS on a Quadro K4000 GPU. [ 20 ] implements cache-oblivious strategy to accelerate ViterbiFilter, that yields a roughly constant performance of 3 GCUPS on an Intel i7 processor and 1.7 GCUPS on AMD Opteron Bulldozer processor.…”
Section: Resultsmentioning
confidence: 99%
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“…The original work [ 2 ] yields 12 GCUPS on MSVFilter and 1.6 GCUPS on ViterbiFilter by single core of an Intel processor. Acceleration via high-end FPGA designs in [ 15 ] yields upto 81 GCUPS for MSV and 3.6 GCUPS for P7Viterbi; GPUHMMER [ 6 ], an outdated acceleration with roughly 1.48 GCUPS, was modified by Lin [ 17 ] to accelerate MSVFilter in HMMER 3.x, which yields upto 32.8 GCUPS on a Quadro K4000 GPU. [ 20 ] implements cache-oblivious strategy to accelerate ViterbiFilter, that yields a roughly constant performance of 3 GCUPS on an Intel i7 processor and 1.7 GCUPS on AMD Opteron Bulldozer processor.…”
Section: Resultsmentioning
confidence: 99%
“…This renders any acceleration attempt for previous versions of HMMER obsolete. Hence alternative architectures such as FPGA [ 15 ] have been explored as an accelerator hardware for MSV and P7Viterbi segments in HMMER 3.x. The Viterbi algorithm was rewritten for parallelization via prefix sums approach on the FPGA and is able to achieve comparable performance for P7Viterbi implemented on dual-core processors.…”
Section: Introductionmentioning
confidence: 99%
“…In the original HMMER3 paper [3], Eddy reports 12 GCUPS for MSV stage, achieved by a single CPU core. Several acceleration efforts exist and report higher performance: (a) an FPGA-based implementation [11] yields upto 81 GCUPS for MSV stage; (b) Lin [13] inherits and modifies a GPU-based implementation of HMMER2 [6] to accelerate MSV stage of HMMER3, which achieves upto 32.8 GCUPS on a Quadro K4000 GPU; (c) [16] claims the first acceleration work on SSV stage of latest HMMER v3.1b2 and reports the maximum performance of 372.1 GCUPS on a GTX570 GPU. To sum up, as shown in Fig.…”
Section: Performance Comparison: Cudampf++ Vs Othersmentioning
confidence: 99%
“…There are only few existing work that aim to accelerate SSV, MSV and P7Viterbi stages of hmmsearch pipeline in HMMER3. Abbas et al [11] re-writes mathematical formulas of MSV and Viterbi algorithms to expose reduction and prefix scan computation patterns which are fitted into the FPGA architecture. In [12], a speculative method is proposed to reduce the number of global memory access on the GPU, which aims to accelerate the MSV stage.…”
Section: Related Workmentioning
confidence: 99%
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