Accelerating jitter tolerance qualification for high speed serial interfaces

We propose a fast method for identifying the jitter tolerance curves of high-speed phase locked loops. The method is based on an adaptive recursion and uses known tail fitting methods to realize a fast optimization combined with a small number of jitter samples. It allows for efficient behavioral simulations, and can also be applied to hardware measurements. A typical modeling example demonstrates applicability to both software and hardware scenarios and achieves simulated measurement times in the range of few hundred milliseconds.

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A holistic methodology for system margining and jitter tolerance optimization in post-silicon validation

Rangel-Patiño

Viveros-Wacher

Rayas‐Sánchez

et al. 2016

2016 IEEE MTT-S Latin America Microwave Conference (LAMC)

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The optimization of receiver analog circuitry in modern high-speed input/output (HSIO) links is a very time consuming post-silicon validation process. Current industrial practices are based on exhaustive enumeration methods to improve either the system margins or the jitter tolerance compliance test. In this paper, these two requirements are addressed in a holistic optimization-based approach. We propose an innovative objective function based on these two metrics. Our method employs Kriging to build a surrogate model based on system margining and jitter tolerance measurements. The proposed method is able to deliver optimal system margins and guarantee jitter tolerance compliance while substantially decreasing the typical post-Si validation time.

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Accelerating jitter tolerance qualification for high speed serial interfaces

Cited by 6 publications

References 8 publications

Accelerating Test, Validation and Debug of High Speed Serial Interfaces

Accelerating Test, Validation and Debug of High Speed Serial Interfaces

A method for fast jitter tolerance analysis of high-speed PLLs

A holistic methodology for system margining and jitter tolerance optimization in post-silicon validation

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