Accelerating Molecular Dynamics Simulations with Reconfigurable Computers

Scrofano, Ronald; Gokhale, Maya; Trouw, Frans; Prasanna, Viktor K.

doi:10.1109/tpds.2007.70777

Cited by 34 publications

(17 citation statements)

References 29 publications

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“…Hardware implementations of MD have been studied with the Anton series of ASIC-based systems (Grossman et al, 2015;Shaw et al, 2007;Shaw et al, 2014;Young et al, 2009) and numerous single FPGA studies (e.g., (Alam et al, 2007;Chiu and Herbordt, 2010;Scrofano et al, 2008)). Details of range-limited pipelines can be found in (Shaw et al, 2007;Chiu and Herbordt, 2010), range-limited communication in (Grossman et al, 2015), and the 3D FFT in (Young et al, 2009).…”

Section: MD Fpgas and Strong Scalingmentioning

confidence: 99%

High Performance Communication on Reconfigurable Clusters

Sheng

Yang

Herbordt

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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High Performance Computing (HPC) has matured to where it is an essential third pillar, along with theory and experiment, in most domains of science and engineering. Communication latency is a key factor that is limiting the performance of HPC, but can be addressed by integrating communication into accelerators. This integration allows accelerators to communicate with each other without CPU interactions, and even bypassing the network stack. Field Programmable Gate Arrays (FPGAs) are the accelerators that currently best integrate communication with computation. The large number of Multi-gigabit Transceivers (MGTs) on most high-end FPGAs can provide high-bandwidth and low-latency inter-FPGA connections. Additionally, the reconfigurable FPGA fabric enables tight coupling between computation kernel and network interface. Our thesis is that an application-aware communication infrastructure for a multi-FPGA system makes substantial progress in solving the HPC communication bottleneck. This dissertation aims to provide an application-aware solution for communication infrastructure for FPGA-centric clusters. Specifically, our solution demonstrates application-awareness across multiple levels in the network stack, including low-level vii link protocols, router microarchitectures, routing algorithms, and applications. We start by investigating the low-level link protocol and the impact of its latency variance on performance. Our results demonstrate that, although some link jitter is always present, we can still assume near-synchronous communication on an FPGAcluster. This provides the necessary condition for statically-scheduled routing. We then propose two novel router microarchitectures for two different kinds of workloads: a wormhole Virtual Channel (VC)-based router for workloads with dynamic communication, and a statically-scheduled Virtual Output Queueing (VOQ)-based router for workloads with static communication. For the first (VC-based) router, we propose a framework that generates application-aware router configurations. Our results show that, by adding application-awareness into router configuration, the network performance of FPGA clusters can be substantially improved. For the second (VOQbased) router, we propose a novel offline collective routing algorithm. This shows a significant advantage over a state-of-the-art collective routing algorithm. We apply our communication infrastructure to a critical strong-scaling HPC kernel, the 3D FFT. The experimental results demonstrate that the performance of our design is faster than that on CPUs and GPUs by at least one order of magnitude (achieving strong scaling for the target applications). Surprisingly, the FPGA cluster performance is similar to that of an ASIC-cluster. We also implement the 3D FFT on another multi-FPGA platform: the Microsoft Catapult II cloud. Its performance is also comparable or superior to CPU and GPU HPC clusters. The second application we investigate is Molecular Dynamics Simulation (MD). We model MD on both FPGA clouds and clusters. We find ...

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Section: MD Fpgas and Strong Scalingmentioning

confidence: 99%

High Performance Communication on Reconfigurable Clusters

Sheng

Yang

Herbordt

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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“…In view of the advancement of computer networking, Scrofano et al 175 have developed another pipeline for MD processes performed on a cluster of FGPAs computation nodes. The hardware design for each FGPA node is similar to that in Fig.…”

Section: Recon¯gurable Computingmentioning

confidence: 99%

Molecular Dynamics Simulation of Iron — A Review

Chui

Liu

et al. 2015

SPIN

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Molecular dynamics (MD) is a technique of atomistic simulation which has facilitated scienti¯c discovery of interactions among particles since its advent in the late 1950s. Its merit lies in incorporating statistical mechanics to allow for examination of varying atomic con¯gurations at nite temperatures. Its contributions to materials science from modeling pure metal properties to designing nanowires is also remarkable. This review paper focuses on the progress of MD in understanding the behavior of iron -in pure metal form, in alloys, and in composite nanomaterials. It also discusses the interatomic potentials and the integration algorithms used for simulating iron in the literature. Furthermore, it reveals the current progress of MD in simulating iron by exhibiting some results in the literature. Finally, the review paper brie°y mentions the development of the hardware and software tools for such large-scale computations.

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“…They can be used to implement complex applications, including floating-point ones [Scrofano et al 2008;Underwood 2004;Woods and VanCourt 2008;Zhuo and Prasanna 2008]. This has sparked the development of floating-point units targeting FPGAs, first for the basic operators mimicking thoses found in microprocessors [Belanovic and Leeser 2002;Louca et al 1996;Shirazi et al 1995], then more recently for operators which are more FPGA-specific, for instance accumulators [Bodnar et al 2006;de Dinechin et al 2008;Luo and Martonosi 2000;Wang et al 2006] or elementary functions Doss and Riley 2004;Pineiro et al 2004].…”

Section: Introduction 1floating Point Acceleration Using Fpgasmentioning

confidence: 99%

Floating-Point Exponentiation Units for Reconfigurable Computing

Dinechin

Echeverría

López‐Vallejo

et al. 2013

ACM Trans. Reconfigurable Technol. Syst.

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The high performance and capacity of current FPGAs makes them suitable as acceleration co-processors. This article studies the implementation, for such accelerators, of the floating-point power function x y as defined by the C99 and IEEE 754-2008 standards, generalized here to arbitrary exponent and mantissa sizes. Last-bit accuracy at the smallest possible cost is obtained thanks to a careful study of the various subcomponents: a floating-point logarithm, a modified floating-point exponential, and a truncated floatingpoint multiplier. A parameterized architecture generator in the open-source FloPoCo project is presented in details and evaluated.

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Accelerating Molecular Dynamics Simulations with Reconfigurable Computers

Cited by 34 publications

References 29 publications

High Performance Communication on Reconfigurable Clusters

High Performance Communication on Reconfigurable Clusters

Molecular Dynamics Simulation of Iron — A Review

Floating-Point Exponentiation Units for Reconfigurable Computing

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