Accelerating pipelined integer and floating-point accumulations in configurable hardware with delayed addition techniques

Abstract

ÐThe speed of arithmetic calculations in configurable hardware is limited by carry propagation, even with the dedicated hardware found in recent FPGAs. This paper proposes and evaluates an approach called delayed addition that reduces the carrypropagation bottleneck and improves the performance of arithmetic calculations. Our approach employs the idea used in Wallace trees to store the results in an intermediate form and delay addition until the end of a repeated calculation such as accumulation or dotproduct; this effectively removes carry propagation overhead from the calculation's critical path. We present both integer and floatingpoint designs that use our technique. Our pipelined integer multiply-accumulate (MAC) design is based on a fairly traditional multiplier design, but with delayed addition as well. This design achieves a 72MHz clock rate on an XC4036xla-9 FPGA and 170MHz clock rate on an XV300epq240-8 FPGA. Next, we present a 32-bit floating-point accumulator based on delayed addition. Here, delayed addition requires a novel alignment technique that decouples the incoming operands from the accumulated result. A conservative version of this design achieves a 40 MHz clock rate on an XC4036xla-9 FPGA and 97MHz clock rate on an XV100epq240-8 FPGA. We also present a 32-bit floating-point accumulator design with compiler-managed overflow avoidance that achieves a 80MHz clock rate on an XC4036xla-9 FPGA and 150MHz clock rate on an XCV100epq240-8 FPGA.

Optimistic Parallelization of Floating-Point Accumulation

“…Previous attempts to pipeline floating-point accumulation, such as [6], do so only at the expense of assuming associativity and thereby producing non-compliant results. In contrast, the techniques introduced here show how to exploit associativity while obtaining results identical to the sequential ordering specified in the program.…”

Ultra-low-power adder stage design for exascale floating point units

“…Thus, power consumption is reduced, but large precision formats require more cycles to complete the operation. The proposal described in Vangal et al [2006] considers delayed addition, as in Luo and Martonosi [2000], for optimizing the delay of large sums. Moreover, authors optimize the SP FP-MAC by adding in 32 base.…”

Floating-Point Exponentiation Units for Reconfigurable Computing

“…They can be used to implement complex applications, including floating-point ones [Scrofano et al 2008;Underwood 2004;Woods and VanCourt 2008;Zhuo and Prasanna 2008]. This has sparked the development of floating-point units targeting FPGAs, first for the basic operators mimicking thoses found in microprocessors [Belanovic and Leeser 2002;Louca et al 1996;Shirazi et al 1995], then more recently for operators which are more FPGA-specific, for instance accumulators [Bodnar et al 2006;de Dinechin et al 2008;Luo and Martonosi 2000;Wang et al 2006] or elementary functions Doss and Riley 2004;Pineiro et al 2004].…”