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Current Systems-On-Chip (SoC)

Abstract-This work presents a new modular and lowcomplexity algorithm for the delineation of the different ECG waves (QRS, P and T peaks, onsets and end). Involving a reduced number of operations per second and having a small memory footprint, this algorithm is intended to perform realtime delineation on resource-constrained embedded systems. The modular design allows the algorithm to automatically adjust the delineation quality in run time to a wide range of modes and sampling rates, from a Ultra-low power mode when no arrhythmia is detected, in which the ECG is sampled at low frequency, to a complete High-accuracy delineation mode in which the ECG is sampled at high frequency and all the ECG fiducial points are detected, in case of arrhythmia. The delineation algorithm has been adjusted using the QT database, providing very high sensitivity and positive predictivity, and validated with the MIT database. The errors in the delineation of all the fiducial points are below the tolerances given by the Common Standards for Electrocardiography (CSE) committee in the High-accuracy mode, except for the P wave onset, for which the algorithm is above the agreed tolerances by only a fraction of the sample duration. The computational load for the ultra-low-power 8-MHz TI MSP430 series microcontroller ranges from 0.2 to 8.5% according to the mode used.

New tendencies envisage multiprocessor systems-on-chips (MPSoCs) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute multiple applications (games, video) while meeting additional design constraints (energy consumption, timeto-market). Moreover, the rise of temperature in the die for MPSoCs can seriously affect their final performance and reliability. In this article, we present a new hardware-software emulation framework that allows designers a complete exploration of the thermal behavior of final MPSoC An initial version of this article was presented in the 2006 IEEE/ACM Design Automation Conference (DAC). This extended version presents several new contributions: (i) Extensions of the description of the developed thermal library and emulated SoC. (ii) Complete overview of related work on MPSoC modeling, testing and thermal-aware design. (iii) Study of different thermal library models to characterize final MPSoC designs. (iv) Illustration of the application of the tool with different floorplans. (v) Evaluation of the impact of employing different packaging technologies in target MPSoCs.