A Complete Network-On-Chip Emulation Framework

Genko, N.; Atienza, David; Micheli, Giovanni De; Mendias, J.M.; Hermida, R.; Catthoor, Francky

doi:10.1109/date.2005.5

Cited by 102 publications

(57 citation statements)

References 16 publications

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“…In this survey, traffic characterization for NoC performance evaluation is highlighted as a key issue. More specifically related to on-chip traffic generation, two main approaches have been studied: deterministic traffic generation, in which the objective is to exactly reproduce the traffic of a given ip [13,19,20] and stochastic traffic generation which uses random sources in place of real ips [17,25,31]. In the deterministic approach, Mahadevan et al introduced, for instance, a trace compiler able to accurately reproduce the traffic of a processor [20].…”

Section: Related Workmentioning

confidence: 99%

Long-range dependence and on-chip processor traffic

Scherrer

Fraboulet

Risset

2009

Microprocessors and Microsystems

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Long-range dependence is a property of stochastic processes that has an important impact on network performance, especially on the buffer usage in routers. We analyze the presence of long-range dependence in on-chip processor traffic and we study the impact of long-range dependence on networks-on-chip. We propose to investigate the presence of long-range dependence in communication traces of processor ips at the cycle-accurate level. We also study the impact of long-range dependence on a real network-on-chip using the SocLib simulation environment and traffic generators of our own. Our experiments show that long-range dependence is not an ubiquitous property of on-chip processor traffic and that its impact on the network-on-chip is highly correlated with the low level communication protocol used.

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Section: Related Workmentioning

confidence: 99%

Long-range dependence and on-chip processor traffic

Scherrer

Fraboulet

Risset

2009

Microprocessors and Microsystems

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“…Much work focus on generating, exploring, evaluating, formalising, and comparing NoC architectures and instantiations [2,5,8,14,22,25,38,39,45,48,52,63]. However, only a few works address guaranteed services [25,39,45], and most works are limited to evaluations of a single small-scale example, or only a few steps of the design flow, as exemplified by the overview in [48].…”

Section: Functional Scalabilitymentioning

confidence: 99%

“…A few NoC design flows have been demonstrated on FPGA [2,22,33,43,52], predominantly using simple media-centric applications like M-JPEG [33] and MPEG-2 [43]. In addition to FPGAs, complete NoC-based SoC ASICs are presented in [7,17,72] together with a post-layout evaluation.…”

Section: Functional Scalabilitymentioning

confidence: 99%

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A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

Hansson

Goossens

2011

Des Autom Embed Syst

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A growing number of applications are integrated on the same System on Chip in the form of hardware and software Intellectual Property (IP). Many applications have firm or soft real-time requirements and require bounds on latency and throughput. To accommodate the growing number of application requirements, the on-chip interconnect must offer scalability on the physical, architectural and functional level.Networks on Chip (NoC) are proposed as a scalable communication architecture that is also able to deliver guaranteed performance. Traditionally, NoCs focus on delivering physical and architectural scalability. The functional scalability, i.e. the ability to satisfy an increasing number of increasingly demanding requirements with a constant cost/performance ratio, is often overlooked. The onus is on the interconnect design flow that translates user requirements to an interconnect instance. While mature tooling exists for many of the IPs, interconnect design flows are an active research area, with few concrete examples, and few large-scale case studies.As the main contribution of this work, we demonstrate a complete operational interconnect design flow for multiple real-time applications, and quantitatively evaluate the functional scalability on two large-scale industrial case studies. We illustrate the steps of the flow, going from requirement specification all the way to simulation of synthesised netlists in a 90 nm and 65 nm low-power standard-cell technology. We show that the interconnect and design flow offer scalability, on the physical, architectural as well as the functional level.

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“…For the NoC topologies design exploration, Genko et al [15] have created an emulation framework, which is implemented on an FPGA. The emulation framework has been designed as a modular NoC programmable platform.…”

Section: Related Workmentioning

confidence: 99%

Towards Architectural Design Space Exploration for Heterogeneous Manycores

Xypolitidis

Shabani

Khandeparkar

et al. 2016

2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

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Abstract-Today many of the high performance embedded processors already contain multiple processor cores and we see heterogeneous manycore architectures being proposed. Therefore it is very desirable to have a fast way to explore various heterogeneous architectures through the use of an architectural design space exploration tool, giving the designer the option to explore design alternatives before the physical implementation.In this paper, we have extended Heracles, a design space exploration tool for (homogeneous) manycore architectures, to incorporate different types of processing cores, and thus allow us to model heterogeneity. Our tool, called the Heterogeneous Heracles System (HHS), can besides the already supported MIPS core also include OpenRISC cores. The new tool retains the possibility available in Heracles to perform register transfer level (RTL) simulations of each explored architecture in Verilog as well as synthesizing it to field-programmable gate arrays (FPGAs). To facilitate the exploration of heterogeneous architectures, we have also extended the graphical user interface (GUI) to support heterogeneity. This GUI provides options to configure the types of core, core settings, memory system and network topology.Some initial results on FPGA utilization are presented from synthesizing both homogeneous and heterogeneous manycore architectures, as well as some benchmark results from both simulated and synthesized architectures.

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A Complete Network-On-Chip Emulation Framework

Abstract: Current Systems-On-Chip (SoC)

Cited by 102 publications

References 16 publications

Long-range dependence and on-chip processor traffic

Long-range dependence and on-chip processor traffic

A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

Towards Architectural Design Space Exploration for Heterogeneous Manycores

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