Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT

Singh, Abhairaj; Fieback, Moritz; Bishnoi, Rajendra; Bradaric, Filip; Gebregiorgis, Anteneh; Joshi, Rajiv V.; Hamdioui, Said

doi:10.1109/itc50671.2022.00085

Cited by 11 publications

(2 citation statements)

References 38 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Optimizations: Compute operations can be used to speed up testing and increase the detection capabilities. For example, in [21], compute operations are used to detect unique RRAM faults in a more efficient manner than could be achieved using only memory operations. As such, the usage of CIM also gives opportunities to increase test efficiency and fault coverage.…”

Section: Directionsmentioning

confidence: 99%

Dependability of Future Edge-AI Processors: Pandora’s Box

Gomony,

Gebregiorgis,

Fieback

et al. 2023

2023 IEEE European Test Symposium (ETS)

Self Cite

View full text Add to dashboard Cite

This paper addresses one of the directions of the HORIZON EU CONVOLVE project being dependability of smart edge processors based on computation-in-memory and emerging memristor devices such as RRAM. It discusses how how this alternative computing paradigm will change the way we used to do manufacturing test. In addition, it describes how these emerging devices inherently suffering from many nonidealities are calling for new solutions in order to ensure accurate and reliable edge computing. Moreover, the paper also covers the security aspects for future edge processors and shows the challenges and the future directions.

show abstract

Section: Directionsmentioning

confidence: 99%

Dependability of Future Edge-AI Processors: Pandora’s Box

Gomony,

Gebregiorgis,

Fieback

et al. 2023

2023 IEEE European Test Symposium (ETS)

Self Cite

View full text Add to dashboard Cite

show abstract

“…• Variation: Variation is the deviation of the resistance value of the memristor after programming from the expected resistance value, which can lead to incorrect computations [29][30][31]. Variation happens mainly due to fabrication imperfections and the stochastic nature of underlying physics.…”

Section: Cim Non-ideality Challengesmentioning

confidence: 99%

Dealing with Non-Idealities in Memristor Based Computation-In-Memory Designs

Gebregiorgis

Singh

Diware

et al. 2022

2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)

View full text Add to dashboard Cite

Computation-In-Memory (CIM) using memristor devices provides an energy-efficient hardware implementation of arithmetic and logic operations for numerous applications, such as neuromorphic computing and database query. However, memristor-based CIM suffers from various non-idealities such as conductance drift, read disturb, wire parasitics, endurance and device degradation. These negatively impact the computation accuracy of CIM. It is therefore essential to deal with these nonidealities and fabrication imperfections in order to harness the full potential of CIM. This paper discusses the non-ideality challenges and provides potential solutions. Furthermore, the paper outlines the potential future directions for CIM architectures.

show abstract

A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing

Copetti,

Fieback,

Gemmeke

et al. 2024

J Electron Test

View full text Add to dashboard Cite

Memristive devices have become promising candidates to complement the CMOS technology, due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability, as well as their capability to implement high-density memories and new computing paradigms. Despite these advantages, memristive devices are susceptible to manufacturing defects that may cause faulty behaviors not observed in CMOS technology, significantly increasing the challenge of testing these novel devices after manufacturing. This work proposes an optimized Design-for-Testability (DfT) strategy based on the introduction of a DfT circuitry that measures the current consumption of Resistive Random Access Memory (ReRAM) cells to detect not only traditional but also unique faults. The new DfT circuitry was validated using a case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library. The obtained results demonstrate the fault detection capability of the proposed strategy with respect to traditional and unique faults. In addition, this paper evaluates the impact related to the DfT circuitry’s introduced overheads as well as the impact of process variation on the resolution of the proposed DfT circuitry.

show abstract

Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT

Cited by 11 publications

References 38 publications

Dependability of Future Edge-AI Processors: Pandora’s Box

Dependability of Future Edge-AI Processors: Pandora’s Box

Dealing with Non-Idealities in Memristor Based Computation-In-Memory Designs

A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing

Contact Info

Product

Resources

About