Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays 2022
DOI: 10.1145/3490422.3502358
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Accelerating SSSP for Power-Law Graphs

Abstract: The single-source shortest path (SSSP) problem is one of the most important and well-studied graph problems widely used in many application domains, such as road navigation, neural image reconstruction, and social network analysis. Although we have known various SSSP algorithms for decades, implementing one for largescale power-law graphs efficiently is still highly challenging today, because ① a work-efficient SSSP algorithm requires priority-order traversal of graph data, ② the priority queue needs to be sca… Show more

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Cited by 18 publications
(5 citation statements)
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References 38 publications
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“…Unlike the eager algorithm, there are no parameters that need to be adjusted, as the removals are performed according to the distances and costs of neighbors. Recent works such as those presented in [17,30,31] validated the effectiveness of that approach in achieving efficient parallelism by partially or fully using the proposed method.…”
Section: Shortest-path Problemmentioning
confidence: 83%
“…Unlike the eager algorithm, there are no parameters that need to be adjusted, as the removals are performed according to the distances and costs of neighbors. Recent works such as those presented in [17,30,31] validated the effectiveness of that approach in achieving efficient parallelism by partially or fully using the proposed method.…”
Section: Shortest-path Problemmentioning
confidence: 83%
“…In our case, this would require t ≈ 4.3 • 10 12 operations and even by exploiting parallelization, it would be prohibitively expensive. The best algorithm for parallel single source shortest paths for powerlaw graphs similar to ours only gives a speedup of 2.4x on a 32-thread CPU [53]. Even with such efficient algorithms, we would require data processing in the order of Teraflops.…”
Section: A Alternative Graph Metricsmentioning
confidence: 96%
“…As for HBM-specific optimizations, [22] presents an HLS design that applies a similar floorplanning strategy and achieves a design frequency of 237 MHz when using 18 HBM channels. The majority of the recent HBM-based accelerators [19], [20], [23] are HLS designs but are not able to get more than 190 MHz and use more than 28 HBM channels. [21] implements a hash join accelerator that uses 32 HBM channels while running at 250 MHz and its random memory accesses are through 256-bit wide AXI interfaces.…”
Section: Related Workmentioning
confidence: 99%
“…Finally, the HBM stacks are physically connected to a datacenter FPGA's bottom die only, making it difficult to spread the resource utilization across multiple FPGA dies to achieve desirable timing closure. To the best of our knowledge, none of the published HBM-based accelerator designs [19], [20], [21], [22], [23] is able to fully utilize the entire bandwidth of the 32 HBM channels.…”
Section: Introductionmentioning
confidence: 99%