Accelerating the Viterbi Algorithm for Profile Hidden Markov Models Using Reconfigurable Hardware

Abstract

Abstract. Profile Hidden Markov Models (PHMMs) are used as a popular tool in bioinformatics for probabilistic sequence database searching. The search operation consists of computing the Viterbi score for each sequence in the database with respect to a given query PHMM. Because of the rapid growth of biological sequence databases, finding fast solutions is of highest importance to research in this area. Unfortunately, the required scan times of currently available sequential software implementations are very high. In this paper we show how reconfigurable hardware can be used as a computational platform to accelerate this application by two orders of magnitude.

Accelerating HMMer on FPGAs using systolic array based architecture

“…The maximum CPUS performance of our design is 130MHz * 25PEs = 3.2GCUPS. The performance of hmmsearch is around from 24 MCUPS [15] …”

“…Plan7 HMM has a feedback loop which makes it possible to describe a string of multiple motif instances in one protein. Many researchers eliminate the feedback loop [1] [15] [11] so as to facilitate the FPGA implementations, which leads to the lost of multi-hit alignments. Jacob, et al also use a systolic array to parallelize the design [1], they got a throughput of 10647 MCUPS, and with the best cast a 190x speedup is achieved.…”

“…Jacob, et al also use a systolic array to parallelize the design [1], they got a throughput of 10647 MCUPS, and with the best cast a 190x speedup is achieved. The early work of Oliver, et al [15] also uses a simplified Plan7 HMM, and it gets a maximum speed-up of 220 with 5.3GCUPS. The work centers main of the PE, and needs to make some introduction about the transmission and emission probs.…”

“…Many solutions [1] [11] [15] are based on the simplified HMM without a rare feedback loop in HMM, while other implementations accelerates full Plan7 HMM [14] [13]. FPGA and MPI are combined into an MPI-HMMER-Boost to achieve a better speedup [8].…”

Preliminary results in accelerating profile HMM search on FPGAs

“…However, no published information exists to perform a fair comparison with our architecture. Oliver et al [11] report an architecture for accelerating the simple Plan 7 HMMER computation. They report a throughput of 5.3 GCUPS, approximately half our throughput on the same FPGA device.…”