Accelerating two-dimensional page walks for virtualized systems

Abstract

Nested paging is a hardware solution for alleviating the software memory management overhead imposed by system virtualization. Nested paging complements existing page walk hardware to form a two-dimensional (2D) page walk, which reduces the need for hypervisor intervention in guest page table management. However, the extra dimension also increases the maximum number of architecturally-required page table references.This paper presents an in-depth examination of the 2D page table walk overhead and options for decreasing it. These options include using the AMD Opteron TM processor's page walk cache to exploit the strong reuse of page entry references. For a mix of server and SPEC R benchmarks, the presented results show a 15%-38% improvement in guest performance by extending the existing page walk cache to also store the nested dimension of the 2D page walk. Caching nested page table translations and skipping multiple page entry references produce an additional 3%-7% improvement.Much of the remaining 2D page walk overhead is due to lowlocality nested page entry references, which result in additional memory hierarchy misses. By using large pages, the hypervisor can eliminate many of these long-latency accesses and further improve the guest performance by 3%-22%.

Selective switching mechanism in virtual machines via support vector machines and transfer learning

“…To avoid this overhead, Intel (Gillespie 2009) introduced its HAP mode, which is called extended page table (EPT). AMD also proposed a similar mechanism, called nested page table (NPT) (Bhargava et al 2008). NPT or EPT extends the guest page tables by adding tables for physical to machine address mapping.…”

“…However, they did not discuss how super pages can affect the performance of SP mode which is more tolerant to TLB misses. Bhargava et al presented the detail implementation of AMD's two dimensional (NPT) structure (Bhargava et al 2008). To reduce page walk penalty, they proposed to cache nested page translations.…”

Dynamic memory paravirtualization transparent to guest OS

“…Extended page tables (EPT) by Intel [8] and nested page tables (NPT) by AMD [6] are recent hardware extensions that assist memory virtualization and reduce the complexity of software memory management. The hardware extensions add an additional level of address translation from guest physical addresses to host physical addresses.…”

“…Although these extensions significantly reduce the VMM intervention on address translation, the two-level paging mechanism does introduce additional page table entry references and thus increase the latency. Bhargava et al discussed a set of techniques to reduce the 2D page walk overhead [6]. Our technique instead can work on the machines without EPT or NPT.…”

“…Intel and AMD have provided hardware extensions, Intel's VT and AMD's SVM, for x86 architecture to support classical full virtualization [5][6][7][8]. Intel's VT provides two kinds of VMX mode for virtualization: VMX root mode and VMX non-root mode.…”