Accelerating video and image processing design for FPGA using HDL coder and simulink

Hai, Jerry Chan Ting; Pun, Ooi Chee; Tan, Wooi-Haw

doi:10.1109/csudet.2015.7446221

Cited by 14 publications

(4 citation statements)

References 5 publications

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“…In literature [1], [2], and [3], the authors proposed alternative approaches by using a Model-Based Design (MBD) that is a practical design methodology and able to develop rapid prototyping by using MAT-LAB/Simulink. In literature [4] and [5], the authors proposed optimization, such as xed-point optimiza-tion, to reduce the area consumption for a lower-cost FPGA board with limited resources.…”

Section: Introductionmentioning

confidence: 99%

“…In literature [4] and [5], the authors proposed optimization, such as xed-point optimiza-tion, to reduce the area consumption for a lower-cost FPGA board with limited resources. Many applications employed only a few conditions without nested loops [1], [2], [3], [4], and [5]. So, this literature cannot be a good candidate for complex models.…”

Section: Introductionmentioning

confidence: 99%

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Model-Based Design Optimization using CDFG for Image Processing on FPGA

Chumpol,

Solod,

Thongnoo

et al. 2023

ECTI-CIT Transactions

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As the automotive industry moves toward autonomous driving and ADAS (Advanced Driver Assistance Systems), Model-Based Design (MBD) is a practical design methodology. It can be used to develop rapid prototyping by using MATLAB and Simulink. The MBD method still has limitations for handling complex models. This paper uses the Control Data Flow Graph (CDFG), an intermediate representation for analyzing complex algorithms, so that suitable optimizations for image processing applications can be implemented on an FPGA. The experimental results show that the proposed CDFG method improved both the area and speed of the edge detection case study compared with the MathWorks Vision HDL toolbox.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Model-Based Design Optimization using CDFG for Image Processing on FPGA

Chumpol,

Solod,

Thongnoo

et al. 2023

ECTI-CIT Transactions

View full text Add to dashboard Cite

show abstract

“…The design of dedicated hardware architectures is traditionally done by using hardware description languages (HDL). However, as proven by different works [25][26][27], higher abstraction level frameworks can support the designer in helping to focus the attention on system functionalities and in reducing time-to-market. This is possible, for example, by using MATLAB/Simulink software [28].…”

Section: Introductionmentioning

confidence: 99%

A Model-Based Design Floating-Point Accumulator. Case of Study: FPGA Implementation of a Support Vector Machine Kernel Function

Bassoli

Bianchi

Munari

2020

Sensors

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Recent research in wearable sensors have led to the development of an advanced platform capable of embedding complex algorithms such as machine learning algorithms, which are known to usually be resource-demanding. To address the need for high computational power, one solution is to design custom hardware platforms dedicated to the specific application by exploiting, for example, Field Programmable Gate Array (FPGA). Recently, model-based techniques and automatic code generation have been introduced in FPGA design. In this paper, a new model-based floating-point accumulation circuit is presented. The architecture is based on the state-of-the-art delayed buffering algorithm. This circuit was conceived to be exploited in order to compute the kernel function of a support vector machine. The implementation of the proposed model was carried out in Simulink, and simulation results showed that it had better performance in terms of speed and occupied area when compared to other solutions. To better evaluate its figure, a practical case of a polynomial kernel function was considered. Simulink and VHDL post-implementation timing simulations and measurements on FPGA confirmed the good results of the stand-alone accumulator.

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“…Furthermore, the increasing complexity of computer vision systems has led designers to resort to higher-level programming and synthesis tools, to shorten the design time. In this regard, Xilinx High-Level Synthesis (HLS) [ 4 ] and Simulink Hardware Description Language (HDL) Coder [ 5 ] are two widely cited tools. The latter is particularly suitable for the design of large computer vision systems, since it incorporates extensive functional verification and the ability to compare with built-in standard algorithms.…”

Section: Introductionmentioning

confidence: 99%

High-Level Synthesis of Online K-Means Clustering Hardware for a Real-Time Image Processing Pipeline

Badawi

Bilal

2019

J. Imaging

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The growing need for smart surveillance solutions requires that modern video capturing devices to be equipped with advance features, such as object detection, scene characterization, and event detection, etc. Image segmentation into various connected regions is a vital pre-processing step in these and other advanced computer vision algorithms. Thus, the inclusion of a hardware accelerator for this task in the conventional image processing pipeline inevitably reduces the workload for more advanced operations downstream. Moreover, design entry by using high-level synthesis tools is gaining popularity for the facilitation of system development under a rapid prototyping paradigm. To address these design requirements, we have developed a hardware accelerator for image segmentation, based on an online K-Means algorithm using a Simulink high-level synthesis tool. The developed hardware uses a standard pixel streaming protocol, and it can be readily inserted into any image processing pipeline as an Intellectual Property (IP) core on a Field Programmable Gate Array (FPGA). Furthermore, the proposed design reduces the hardware complexity of the conventional architectures by employing a weighted instead of a moving average to update the clusters. Experimental evidence has also been provided to demonstrate that the proposed weighted average-based approach yields better results than the conventional moving average on test video sequences. The synthesized hardware has been tested in real-time environment to process Full HD video at 26.5 fps, while the estimated dynamic power consumption is less than 90 mW on the Xilinx Zynq-7000 SOC.

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Accelerating video and image processing design for FPGA using HDL coder and simulink

Cited by 14 publications

References 5 publications

Model-Based Design Optimization using CDFG for Image Processing on FPGA

Model-Based Design Optimization using CDFG for Image Processing on FPGA

A Model-Based Design Floating-Point Accumulator. Case of Study: FPGA Implementation of a Support Vector Machine Kernel Function

High-Level Synthesis of Online K-Means Clustering Hardware for a Real-Time Image Processing Pipeline

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