Acceleration of decision tree searching for IP traffic classification

Luo, Yan; Xiang, Ke Jun; Li, Sanping

doi:10.1145/1477942.1477949

Cited by 34 publications

(28 citation statements)

References 17 publications

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“…Jedhe et al [15] realize the DCFL architecture in their entire firewall implementation on a Xilinx Virtex 2 Pro FPGA, using a memory intensive approach, as opposed to the logic intensive one, so that on-the-fly update is possible. Two recent works [24], [25] discuss several issues in implementing decisiontree-based packet classification algorithms on FPGA, with different motivations. Luo et al [24] propose a method called explicit range search to allow more cuts per node than the Hyper Cuts algorithm.…”

Section: Related Workmentioning

confidence: 99%

“…Two recent works [24], [25] discuss several issues in implementing decisiontree-based packet classification algorithms on FPGA, with different motivations. Luo et al [24] propose a method called explicit range search to allow more cuts per node than the Hyper Cuts algorithm. Based on the cost of increased memory utilization, the tree height is radically reduced.At each internal node in order to find which child node to traverse it is needed to determine the a varying number of memory accesses, which may be infeasible for pipelining.…”

Section: Related Workmentioning

confidence: 99%

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FPGA Based Packet Classification Using Multi-Pipeline Architecture

Raaj¹

2015

WCMC

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This paper proposes a decision-tree-based linear multi-pipeline architecture on FPGA's for packet sorting. We reflect on the next-generation packet classification problems where more than 5-tuple packet header fields has been classified. From traditional fixed 5-tuple matching, Multi-field packet classification has been evolved for flexible matching with arbitrary combination of numerous packet header fields. The recently proposed Open Flow switching requires classifying each packet using up to 12-tuple packet header fields. It become a great task to develop scalable solutions for next-generation packet classification that support larger rule sets, additional packet header fields and higher throughput. This paper proposes a 2-D multi-pipeline decision-tree-based architecture for next-generation packet classification which exploits the abundant parallelism and other desirable features such as current field-programmable gate arrays (FPGAs),. We propose several optimization techniques for the state-of-the-art decision-tree-based algorithm by examine the various traditional 5-tuple packet classification methods. By using set of 12-tuple rules, the framework has been developed to partition the rule set into multiple subsets each of which is built into an optimized decision tree. To maximize the memory utilization. a tree-to-pipeline mapping scheme is carefully designed while underneath high throughput. Our proposed architecture can store up to 1K synthetic 12-tuple rules or 10K real-life 5-tuple rules in on-chip memory of a single up to date FPGA, and maintain 80 or 40 Gbps throughput for least packets of size (40 bytes) respectively. To utilize the memory properly and to sustaining high throughput, a mapping scheme based on tree-to-pipeline is designed carefully. This paper deal with the profuse parallelism and other preferred features provided by present field-programmable gate arrays and propose a 2-D multi-pipeline decision tree based architecture for next-generation packet sorting. The Verilog Hardware description languages (VHDL) are used to design the proposed architecture and synthesized using Xilinx Software.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

FPGA Based Packet Classification Using Multi-Pipeline Architecture

Raaj¹

2015

WCMC

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“…Two recent works [9,13] discuss several issues on implementing decision-tree-based packet classification algorithms on FPGA, with different motivations. Luo et al [13] propose a method called explicit range search to allow more cuts per node than the HyperCuts algorithm.…”

Section: Related Work Based On Fpgasmentioning

confidence: 99%

“…Luo et al [13] propose a method called explicit range search to allow more cuts per node than the HyperCuts algorithm. The tree height is dramatically reduced at the cost of increased memory consumption.…”

Section: Related Work Based On Fpgasmentioning

confidence: 99%

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Large-scale wire-speed packet classification on FPGAs

Jiang

Prasanna

2009

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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Multi-field packet classification is a key enabling function of a variety of network applications, such as firewall processing, Quality of Service differentiation, traffic billing, and other value added services. Although a plethora of research has been done in this area, wire-speed packet classification while supporting large rule sets remains difficult. This paper exploits the features provided by current FPGAs and proposes a decision-tree-based, two-dimensional dual-pipeline architecture for multi-field packet classification. To fit the current largest rule set in the on-chip memory of the FPGA device, we propose several optimization techniques for the stateof-the-art decision-tree-based algorithm, so that the memory requirement is almost linear with the number of rules. Specialized logic is developed to support varying number of branches at each decision tree node. A tree-to-pipeline mapping scheme is carefully designed to maximize the memory utilization. Since our architecture is linear and memorybased, on-the-fly update without disturbing the ongoing operations is feasible. The implementation results show that our architecture can store 10K real-life rules in on-chip memory of a single Xilinx Virtex-5 FPGA, and sustain 80 Gbps (i.e. 2× OC-768 rate) throughput for minimum size (40 bytes) packets. To the best of our knowledge, this work is the first FPGA-based packet classification engine that achieves wire-speed throughput while supporting 10K unique rules.

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