Acceleration of Transition Test Generation for Acyclic Sequential Circuits Utilizing Constrained Combinational Stuck-At Test Generation

Iwagaki, Tsuyoshi; Ohtake, Satoshi; Fujiwara, Hideo

doi:10.1109/ets.2005.4

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Lemma 13: Let X and Y Denote Two Different Primary Inputs Of2

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Cited by 2 publications

(2 citation statements)

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“…To avoid conflicts during sequence transformation Γ to obtain the two-pattern test from the test pattern generated on C E (S A ) [12], v 2…”

Section: Lemma 13: Let X and Y Denote Two Different Primary Inputs Ofmentioning

confidence: 99%

See 1 more Smart Citation

Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on k-Notation

Ooi¹,

Clouqueur²,

Fujiwara

2007

IEICE Transactions on Information and Systems

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In this paper, we discuss the relationship between the test generation complexity for path delay faults (PDFs) and that for stuck-at faults (SAFs) in combinational and sequential circuits using the recently introduced τ k-notation. On the other hand, we also introduce a class of cyclic sequential circuits that are easily testable, namely two-column distributive state-shiftable finite state machine realizations (2CD-SSFSM). Then, we discuss the relevant conjectures and unsolved problems related to the test generation for sequential circuits with PDFs under different clock schemes and test generation models.

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“…To avoid conflicts during sequence transformation Γ to obtain the two-pattern test from the test pattern generated on C E (S A ) [12], v 2…”

Section: Lemma 13: Let X and Y Denote Two Different Primary Inputs Ofmentioning

confidence: 99%

“…y) in the TEM. The idea of pattern-dependency was introduced in [12]. Figure 6 shows the transformations of an acyclic sequential circuit into its pattern-dependency circuit to represent its test generation problem for PDFs based on the test generation for SAFs.…”

Section: Lemma 13: Let X and Y Denote Two Different Primary Inputs Ofmentioning

confidence: 99%

Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on k-Notation

Ooi¹,

Clouqueur²,

Fujiwara

2007

IEICE Transactions on Information and Systems

Self Cite

View full text Add to dashboard Cite

show abstract

A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits

Iwagaki

Ohtake

Fujiwara

2006

2006 IFIP International Conference on Very Large Scale Integration

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Acceleration of Transition Test Generation for Acyclic Sequential Circuits Utilizing Constrained Combinational Stuck-At Test Generation

Cited by 2 publications

References 16 publications

Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on k-Notation

Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on k-Notation

A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits

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