Access-in-turn test architecture for low-power test application

Wang, Weizheng; Jin-cheng, Wang; Wang, Zengyun; Xiang, Lingyun

doi:10.1080/00207217.2016.1218062

Cited by 3 publications

(2 citation statements)

References 26 publications

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“…Advanced design for testability (DFT) methods make manufacturing test and online debugging of chips easier and cheaper by embedding some logic structures such as scan chain, decompressor, test response compactor and X -masker into the circuit at the design stage, so they are particularly popular in the semiconductor industry. The scan design is the most universal DFT methodology which replaces internal flip-flops with the scan cells and makes the automatic test pattern generation (ATPG) very efficient [13,14]. At present, the vast majority of integrated circuits have introduced scan chains to improve the testability of the chip including the controllability and observability [14].…”

Section: Introductionmentioning

confidence: 99%

A Novel Secure Scan Design Based on Delayed Physical Unclonable Function

Wang¹,

Gong²,

Wang³

et al. 2023

Computers, Materials &Amp; Continua

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The advanced integrated circuits have been widely used in various situations including the Internet of Things, wireless communication, etc. But its manufacturing process exists unreliability, so cryptographic chips must be rigorously tested. Due to scan testing provides high test coverage, it is applied to the testing of cryptographic integrated circuits. However, while providing good controllability and observability, it also provides attackers with a backdoor to steal keys. In the text, a novel protection scheme is put forward to resist scan-based attacks, in which we first use the responses generated by a strong physical unclonable function circuit to solidify fuseantifuse structures in a non-linear shift register (NLSR), then determine the scan input code according to the configuration of the fuse-antifuse structures and the styles of connection between the NLSR cells and the scan cells. If the key is right, the chip can be tested normally; otherwise, the data in the scan chain cannot be propagated normally, it is also impossible for illegal users to derive the desired scan data. The proposed technique not only enhances the security of cryptographic chips, but also incurs acceptable overhead.

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Section: Introductionmentioning

confidence: 99%

A Novel Secure Scan Design Based on Delayed Physical Unclonable Function

Wang¹,

Gong²,

Wang³

et al. 2023

Computers, Materials &Amp; Continua

View full text Add to dashboard Cite

show abstract

“…Such DFT technology can control and observe the state of flip-flops by replacing them with scan cells, and the controllability and observability of integrated circuit (IC) is improved dramatically. As a result, automatic test pattern generation (ATPG) becomes effortless, and high fault coverage and little test application time can be achieved easily [14,15,16]. Nevertheless, scan design opens out a backdoor for illegal user to steal encryption key from cryptographic chip.…”

Section: Introductionmentioning

confidence: 99%

Enhancing Sensor Network Security with Improved Internal Hardware Design

Wang

Deng

Jin

2019

Sensors

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With the rapid development of the Internet-of-Things (IoT), sensors are being widely applied in industry and human life. Sensor networks based on IoT have strong Information transmission and processing capabilities. The security of sensor networks is progressively crucial. Cryptographic algorithms are widely used in sensor networks to guarantee security. Hardware implementations are preferred, since software implementations offer lower throughout and require more computational resources. Cryptographic chips should be tested in a manufacturing process and in the field to ensure their quality. As a widely used design-for-testability (DFT) technique, scan design can enhance the testability of the chips by improving the controllability and observability of the internal flip-flops. However, it may become a backdoor to leaking sensitive information related to the cipher key, and thus, threaten the security of a cryptographic chip. In this paper, a secure scan test architecture was proposed to resist scan-based noninvasive attacks on cryptographic chips with boundary scan design. Firstly, the proposed DFT architecture provides the scan chain reset mechanism by gating a mode-switching detection signal into reset input of scan cells. The contents of scan chains will be erased when the working mode is switched between test mode and functional mode, and thus, it can deter mode-switching based noninvasive attacks. Secondly, loading the secret key into scan chains of cryptographic chips is prohibited in the test mode. As a result, the test-mode-only scan attack can also be thwarted. On the other hand, shift operation under functional mode is disabled to overcome scan attack in the functional mode. The proposed secure scheme ensures the security of cryptographic chips for sensor networks with extremely low area penalty.

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Ensuring Cryptography Chips Security by Preventing Scan-Based Side-Channel Attacks With Improved DFT Architecture

Wang

et al. 2022

IEEE Trans. Syst. Man Cybern, Syst.

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Access-in-turn test architecture for low-power test application

Cited by 3 publications

References 26 publications

A Novel Secure Scan Design Based on Delayed Physical Unclonable Function

A Novel Secure Scan Design Based on Delayed Physical Unclonable Function

Enhancing Sensor Network Security with Improved Internal Hardware Design

Ensuring Cryptography Chips Security by Preventing Scan-Based Side-Channel Attacks With Improved DFT Architecture

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