Accounting for memory bank contention and delay in high-bandwidth multiprocessors

Abstract

Abstract-For years, the computation rate of processors has been much faster than the access rate of memory banks, and this divergence in speeds has been constantly increasing in recent years. As a result, several shared-memory multiprocessors consist of more memory banks than processors. The object of this paper is to provide a simple model (with only a few parameters) for the design and analysis of irregular parallel algorithms that will give a reasonable characterization of performance on such machines. For this purpose, we extend Valiant's bulk-synchronous parallel (BSP) model with two parameters: a parameter for memory bank delay, the minimum time for servicing requests at a bank, and a parameter for memory bank expansion, the ratio of the number of banks to the number of processors. We call this model the (d, x)-BSP. We show experimentally that the (d, x)-BSP captures the impact of bank contention and delay on the CRAY C90 and J90 for irregular access patterns, without modeling machine-specific details of these machines. The model has clarified the performance characteristics of several unstructured algorithms on the CRAY C90 and J90, and allowed us to explore tradeoffs and optimizations for these algorithms. In addition to modeling individual algorithms directly, we also consider the use of the (d, x)-BSP as a bridging model for emulating a very high-level abstract model, the Parallel Random Access Machine (PRAM). We provide matching upper and lower bounds for emulating the EREW and QRQW PRAMs on the (d, x)-BSP.

Quantifying and resolving remote memory access contention on hardware DSM multiprocessors

“…[1,3,5]). However, most of these works quantified contention either by detailed simulation or with analytical modelling.…”

“…Blelloch et.al. [1] developed a formal model for analyzing memory bank contention on shared memory multiprocessors in which processors access memory via a switching network. Frank et.al.…”

“…The experiments were conducted on the NCSA Origin2000 at the University of Illinois at Urbana-Champaign. other coherence protocol transactions directed to that node 1 .…”

“…This information is collected conveniently in hardware page reference counters, which are available in commercial DSM systems such as the SGI Origin2000 [9] and the Sun Wildfire [6]. The most valuable aspect of this 1 We use the term node to signify the basic building block of a hardware DSM multiprocessor. A node may have one or more processors.…”

Memory bank conflict reduction for embedded multimedia applications

“…Over the past years, memory bank conflict has been studied extensively in the realm of supercomputer [1,2,5,6]. Although many solutions have been proposed [8,9,10,11,12], most of them are designed with the supercomputer in mind and, therefore, not suitable for EMAs. In this work, we first perform a detailed analysis on the impact of memory bank conflict on the performance of EMAs.…”